seg_7.v

这程序是利用状态机来控制交通灯verilog码

module seg_7(clk,scan,qh,ql,seg);
input[3:0]qh,ql;
input clk;
output[7:0] seg;
output[7:0] scan;

reg [3:0]temp;
reg[7:0] seg;
reg[7:0] scan;
reg [1:0] a;

always@(posedge clk)
begin
	if(a==1)
	begin a<=0;end
	else
	begin a<=a+1;end
end

always@(a)
begin
	case(a)
	2'd0:begin scan<=8'b1011_1111;temp<=qh;end
	2'd1:begin scan<=8'b0111_1111;temp<=ql;end
	endcase
end

/*always@(scan)
begin
	case(scan)
		8'b1011_1111:temp<=qh;
		8'b0111_1111:temp<=ql;
		default:temp<=4'bxxxx;
	endcase
end*/

always @(temp)
begin
	case(temp)						//七段译码
		4'h0:seg <= 8'hc0;				//显示0
		4'h1:seg <= 8'hf9;				//显示1
		4'h2:seg <= 8'ha4;				//显示2
		4'h3:seg <= 8'hb0;				//显示3
		4'h4:seg <= 8'h99;				//显示4
		4'h5:seg <= 8'h92;				//显示5
		4'h6:seg <= 8'h82;				//显示6
		4'h7:seg <= 8'hf8;				//显示7
		4'h8:seg <= 8'h80;				//显示8
		4'h9:seg <= 8'h90;				//显示9
		default:seg<=8'b11111111;
	endcase
end

endmodule