jiaotongdeng.v.bak

这程序是利用状态机来控制交通灯verilog码

module jiaotongdeng(clk,clr,qh,ql,ra,ya,ga,rb,yb,gb);
input clk,clr;
//output[1:0] scan;
//output[6:0] seg7;
output ra,ya,ga,rb,yb,gb;
output[3:0] qh,ql;

reg clk1khz,clk1hz;
reg count1,count2;
reg a;                  //倒计时赋值标志位
reg[3:0] qh,ql;         //计数的高位和低位
reg ra,ya,ga,rb,yb,gb;


reg[1:0] CS,NS;
parameter[1:0]
		st1=2'b00,
		st2=2'b01,
		st3=2'b10,
		st4=2'b11;
		
/*always @(posedge clk)    //1KHZ分频
begin
	if(count1==9999)
		begin
		clk1khz<=~clk1khz;
		count1<=0;
		end
	else
		count1<=count1+1;
end

always @(posedge clk1khz)  //1HZ分频
begin
	if(count2==499)
		begin
		clk1hz<=~clk1hz;
		count2<=0;
		end
	else
		count2<=count2+1;
end
*/
always @(posedge clk)  //状态转换
begin
	if(clr)
	CS<=st1;
	else
	CS<=NS;
end

always @(qh or ql)
begin
	NS<=2'bxx;
	case(CS)
		st1:begin
				if(qh==0&&ql==0) 
				NS<=st2;
				else
				NS<=st1;
			end
		st2:begin
				if(qh==0&&ql==0) 
				NS<=st3;
				else
				NS<=st2;
			end
		st3:begin
				if(qh==0&&ql==0) 
				NS<=st4;
				else
				NS<=st3;
			end
		st4:begin
				if(qh==0&&ql==0) 
				NS<=st1;
				else
				NS<=st4;
			end
	endcase
end

always @(posedge clk)
begin
	case(NS)
		st1:begin
				{ra,ya,ga,rb,yb,gb}<=6'b100001;
/*				if(a==0)        //如果倒计时没有赋值
					begin
					qh<=4'b0010;
					ql<=4'b0100;
					a<=1;
					end
				else
					begin
*/						if(qh==0&&ql==0)
							begin
							qh<=4'b0010;
							ql<=4'b0100;
							end
						else 
							begin
								if(ql==0)
									begin
									ql<=4'b1001;
									qh<=qh-1;
									end
								else
									begin
									ql<=ql-1;
									end
							end
//					end
			end

		st2:begin
				{ra,ya,ga,rb,yb,gb}<=6'b010001;
				if(a==0)        //如果倒计时没有赋值
					begin
					qh<=4'b0000;
					ql<=4'b0100;
					a<=1;
					end
				else
					begin
						if(ql==0)
							begin
							a=0;
							end
						else
							begin
							ql<=ql-1;
							end
					end
			end		
			
		st3:begin
				{ra,ya,ga,rb,yb,gb}<=6'b001100;
				if(a==0)        //如果倒计时没有赋值
					begin
					qh<=4'b0010;
					ql<=4'b0100;
					a<=1;
					end
				else
					begin
						if(ql==0)
							begin
								if(qh!==0)
									begin
									ql=4'b0100;
									qh<=qh-1;
									end
								else
									begin
									a=0;
									end
							end
						else
							begin
							ql<=ql-1;
							end
					end
			end
				
		st4:begin
				{ra,ya,ga,rb,yb,gb}<=6'b001010;
				if(a==0)        //如果倒计时没有赋值
					begin
					qh<=4'b0000;
					ql<=4'b0100;
					a<=1;
					end
				else
					begin
						if(ql==0)
							begin
							a=0;
							end
						else
							begin
							ql<=ql-1;
							end
					end
			end	
		endcase			
end
endmodule