jiaotongdeng.sim.rpt

这程序是利用状态机来控制交通灯verilog码

; |jiaotongdeng|ql[2]        ; |jiaotongdeng|ql[2]        ; pin_out          ;
; |jiaotongdeng|ql[3]        ; |jiaotongdeng|ql[3]        ; pin_out          ;
; |jiaotongdeng|ra           ; |jiaotongdeng|ra           ; pin_out          ;
; |jiaotongdeng|ya           ; |jiaotongdeng|ya           ; pin_out          ;
; |jiaotongdeng|ga           ; |jiaotongdeng|ga           ; pin_out          ;
; |jiaotongdeng|rb           ; |jiaotongdeng|rb           ; pin_out          ;
; |jiaotongdeng|yb           ; |jiaotongdeng|yb           ; pin_out          ;
; |jiaotongdeng|gb           ; |jiaotongdeng|gb           ; pin_out          ;
; |jiaotongdeng|CS~4         ; |jiaotongdeng|CS~4         ; out0             ;
; |jiaotongdeng|Selector0~4  ; |jiaotongdeng|Selector0~4  ; out0             ;
; |jiaotongdeng|Selector0~5  ; |jiaotongdeng|Selector0~5  ; out0             ;
; |jiaotongdeng|Selector0~6  ; |jiaotongdeng|Selector0~6  ; out0             ;
; |jiaotongdeng|Selector1~4  ; |jiaotongdeng|Selector1~4  ; out0             ;
; |jiaotongdeng|Selector1~5  ; |jiaotongdeng|Selector1~5  ; out0             ;
; |jiaotongdeng|Selector1~6  ; |jiaotongdeng|Selector1~6  ; out0             ;
; |jiaotongdeng|Selector2~4  ; |jiaotongdeng|Selector2~4  ; out0             ;
; |jiaotongdeng|Selector2~5  ; |jiaotongdeng|Selector2~5  ; out0             ;
; |jiaotongdeng|Selector2~6  ; |jiaotongdeng|Selector2~6  ; out0             ;
; |jiaotongdeng|Selector3~4  ; |jiaotongdeng|Selector3~4  ; out0             ;
; |jiaotongdeng|Selector3~5  ; |jiaotongdeng|Selector3~5  ; out0             ;
; |jiaotongdeng|Selector3~6  ; |jiaotongdeng|Selector3~6  ; out0             ;
; |jiaotongdeng|Selector6~5  ; |jiaotongdeng|Selector6~5  ; out0             ;
; |jiaotongdeng|Selector6~7  ; |jiaotongdeng|Selector6~7  ; out0             ;
; |jiaotongdeng|Selector6~9  ; |jiaotongdeng|Selector6~9  ; out0             ;
; |jiaotongdeng|Selector7~5  ; |jiaotongdeng|Selector7~5  ; out0             ;
; |jiaotongdeng|Selector7~7  ; |jiaotongdeng|Selector7~7  ; out0             ;
; |jiaotongdeng|Selector7~9  ; |jiaotongdeng|Selector7~9  ; out0             ;
; |jiaotongdeng|Selector8~5  ; |jiaotongdeng|Selector8~5  ; out0             ;
; |jiaotongdeng|Selector8~6  ; |jiaotongdeng|Selector8~6  ; out0             ;
; |jiaotongdeng|Selector8~7  ; |jiaotongdeng|Selector8~7  ; out0             ;
; |jiaotongdeng|Selector8~8  ; |jiaotongdeng|Selector8~8  ; out0             ;
; |jiaotongdeng|Selector8~9  ; |jiaotongdeng|Selector8~9  ; out0             ;
; |jiaotongdeng|Selector9~5  ; |jiaotongdeng|Selector9~5  ; out0             ;
; |jiaotongdeng|Selector9~6  ; |jiaotongdeng|Selector9~6  ; out0             ;
; |jiaotongdeng|Selector9~7  ; |jiaotongdeng|Selector9~7  ; out0             ;
; |jiaotongdeng|Selector9~8  ; |jiaotongdeng|Selector9~8  ; out0             ;
; |jiaotongdeng|Selector9~9  ; |jiaotongdeng|Selector9~9  ; out0             ;
; |jiaotongdeng|Selector10~5 ; |jiaotongdeng|Selector10~5 ; out0             ;
; |jiaotongdeng|Selector10~6 ; |jiaotongdeng|Selector10~6 ; out0             ;
; |jiaotongdeng|Selector10~7 ; |jiaotongdeng|Selector10~7 ; out0             ;
; |jiaotongdeng|Selector10~8 ; |jiaotongdeng|Selector10~8 ; out0             ;
; |jiaotongdeng|Selector10~9 ; |jiaotongdeng|Selector10~9 ; out0             ;
; |jiaotongdeng|Selector11~5 ; |jiaotongdeng|Selector11~5 ; out0             ;
; |jiaotongdeng|Selector11~6 ; |jiaotongdeng|Selector11~6 ; out0             ;
; |jiaotongdeng|Selector11~7 ; |jiaotongdeng|Selector11~7 ; out0             ;
; |jiaotongdeng|Selector11~8 ; |jiaotongdeng|Selector11~8 ; out0             ;
; |jiaotongdeng|Selector11~9 ; |jiaotongdeng|Selector11~9 ; out0             ;
; |jiaotongdeng|Add0~25      ; |jiaotongdeng|Add0~25      ; out0             ;
; |jiaotongdeng|Add0~26      ; |jiaotongdeng|Add0~26      ; out0             ;
; |jiaotongdeng|Add0~28      ; |jiaotongdeng|Add0~28      ; out0             ;
; |jiaotongdeng|Add0~29      ; |jiaotongdeng|Add0~29      ; out0             ;
; |jiaotongdeng|Add0~31      ; |jiaotongdeng|Add0~31      ; out0             ;
; |jiaotongdeng|Add1~25      ; |jiaotongdeng|Add1~25      ; out0             ;
; |jiaotongdeng|Add1~26      ; |jiaotongdeng|Add1~26      ; out0             ;
; |jiaotongdeng|Add1~27      ; |jiaotongdeng|Add1~27      ; out0             ;
; |jiaotongdeng|Add1~28      ; |jiaotongdeng|Add1~28      ; out0             ;
; |jiaotongdeng|Add1~29      ; |jiaotongdeng|Add1~29      ; out0             ;
; |jiaotongdeng|Add1~30      ; |jiaotongdeng|Add1~30      ; out0             ;
; |jiaotongdeng|Add1~31      ; |jiaotongdeng|Add1~31      ; out0             ;
; |jiaotongdeng|Equal0~33    ; |jiaotongdeng|Equal0~33    ; out0             ;
; |jiaotongdeng|Equal1~33    ; |jiaotongdeng|Equal1~33    ; out0             ;
+----------------------------+----------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                 ;
+---------------------------+---------------------------+------------------+
; Node Name                 ; Output Port Name          ; Output Port Type ;
+---------------------------+---------------------------+------------------+
; |jiaotongdeng|qh~4        ; |jiaotongdeng|qh~4        ; out              ;
; |jiaotongdeng|qh~5        ; |jiaotongdeng|qh~5        ; out              ;
; |jiaotongdeng|qh~8        ; |jiaotongdeng|qh~8        ; out              ;
; |jiaotongdeng|qh~9        ; |jiaotongdeng|qh~9        ; out              ;
; |jiaotongdeng|qh[3]~reg0  ; |jiaotongdeng|qh[3]~reg0  ; regout           ;
; |jiaotongdeng|qh[2]~reg0  ; |jiaotongdeng|qh[2]~reg0  ; regout           ;
; |jiaotongdeng|clr         ; |jiaotongdeng|clr         ; out              ;
; |jiaotongdeng|qh[2]       ; |jiaotongdeng|qh[2]       ; pin_out          ;
; |jiaotongdeng|qh[3]       ; |jiaotongdeng|qh[3]       ; pin_out          ;
; |jiaotongdeng|Selector4~5 ; |jiaotongdeng|Selector4~5 ; out0             ;
; |jiaotongdeng|Selector4~6 ; |jiaotongdeng|Selector4~6 ; out0             ;
; |jiaotongdeng|Selector4~7 ; |jiaotongdeng|Selector4~7 ; out0             ;
; |jiaotongdeng|Selector4~8 ; |jiaotongdeng|Selector4~8 ; out0             ;
; |jiaotongdeng|Selector4~9 ; |jiaotongdeng|Selector4~9 ; out0             ;
; |jiaotongdeng|Selector5~5 ; |jiaotongdeng|Selector5~5 ; out0             ;
; |jiaotongdeng|Selector5~6 ; |jiaotongdeng|Selector5~6 ; out0             ;
; |jiaotongdeng|Selector5~7 ; |jiaotongdeng|Selector5~7 ; out0             ;
; |jiaotongdeng|Selector5~8 ; |jiaotongdeng|Selector5~8 ; out0             ;
; |jiaotongdeng|Selector5~9 ; |jiaotongdeng|Selector5~9 ; out0             ;
; |jiaotongdeng|Selector6~6 ; |jiaotongdeng|Selector6~6 ; out0             ;
; |jiaotongdeng|Selector6~8 ; |jiaotongdeng|Selector6~8 ; out0             ;
; |jiaotongdeng|Selector7~6 ; |jiaotongdeng|Selector7~6 ; out0             ;
; |jiaotongdeng|Selector7~8 ; |jiaotongdeng|Selector7~8 ; out0             ;
; |jiaotongdeng|Add0~27     ; |jiaotongdeng|Add0~27     ; out0             ;
; |jiaotongdeng|Add0~30     ; |jiaotongdeng|Add0~30     ; out0             ;
+---------------------------+---------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                 ;
+---------------------------+---------------------------+------------------+
; Node Name                 ; Output Port Name          ; Output Port Type ;
+---------------------------+---------------------------+------------------+
; |jiaotongdeng|qh~4        ; |jiaotongdeng|qh~4        ; out              ;
; |jiaotongdeng|qh~5        ; |jiaotongdeng|qh~5        ; out              ;
; |jiaotongdeng|qh~8        ; |jiaotongdeng|qh~8        ; out              ;
; |jiaotongdeng|qh~9        ; |jiaotongdeng|qh~9        ; out              ;
; |jiaotongdeng|qh[3]~reg0  ; |jiaotongdeng|qh[3]~reg0  ; regout           ;
; |jiaotongdeng|qh[2]~reg0  ; |jiaotongdeng|qh[2]~reg0  ; regout           ;
; |jiaotongdeng|qh[2]       ; |jiaotongdeng|qh[2]       ; pin_out          ;
; |jiaotongdeng|qh[3]       ; |jiaotongdeng|qh[3]       ; pin_out          ;
; |jiaotongdeng|Selector4~5 ; |jiaotongdeng|Selector4~5 ; out0             ;
; |jiaotongdeng|Selector4~6 ; |jiaotongdeng|Selector4~6 ; out0             ;
; |jiaotongdeng|Selector4~7 ; |jiaotongdeng|Selector4~7 ; out0             ;
; |jiaotongdeng|Selector4~8 ; |jiaotongdeng|Selector4~8 ; out0             ;
; |jiaotongdeng|Selector4~9 ; |jiaotongdeng|Selector4~9 ; out0             ;
; |jiaotongdeng|Selector5~5 ; |jiaotongdeng|Selector5~5 ; out0             ;
; |jiaotongdeng|Selector5~6 ; |jiaotongdeng|Selector5~6 ; out0             ;
; |jiaotongdeng|Selector5~7 ; |jiaotongdeng|Selector5~7 ; out0             ;
; |jiaotongdeng|Selector5~8 ; |jiaotongdeng|Selector5~8 ; out0             ;
; |jiaotongdeng|Selector5~9 ; |jiaotongdeng|Selector5~9 ; out0             ;
; |jiaotongdeng|Selector6~6 ; |jiaotongdeng|Selector6~6 ; out0             ;
; |jiaotongdeng|Selector6~8 ; |jiaotongdeng|Selector6~8 ; out0             ;
; |jiaotongdeng|Selector7~6 ; |jiaotongdeng|Selector7~6 ; out0             ;
; |jiaotongdeng|Selector7~8 ; |jiaotongdeng|Selector7~8 ; out0             ;
; |jiaotongdeng|Add0~27     ; |jiaotongdeng|Add0~27     ; out0             ;
; |jiaotongdeng|Add0~30     ; |jiaotongdeng|Add0~30     ; out0             ;
+---------------------------+---------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Jan 14 16:40:25 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng
Info: Using vector source file "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      81.34 %
Info: Number of transitions in simulation is 7139
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 97 megabytes of memory during processing
    Info: Processing ended: Wed Jan 14 16:40:26 2009
    Info: Elapsed time: 00:00:01