jishuqi.rpt

在max_plus2和FPGA实验箱上实现频率计的功能

Project Information        d:\luogical  experiment\the 8st\pinlvji\jishuqi.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 07/04/2007 15:10:41

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

jishuqi   EPM7032LC44-6    3        24       0      24      0           75 %

User Pins:                 3        24       0  



Project Information        d:\luogical  experiment\the 8st\pinlvji\jishuqi.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CLR_L' chosen for auto global Clear


Project Information        d:\luogical  experiment\the 8st\pinlvji\jishuqi.rpt

** FILE HIERARCHY **



|09jishuqi:4|
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Device-Specific Information:d:\luogical  experiment\the 8st\pinlvji\jishuqi.rpt
jishuqi

***** Logic for device 'jishuqi' compiled without errors.




Device: EPM7032LC44-6

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF

              R                                
              E                                
              S                                
              E              C                 
              R              L                 
              V        V  G  R  G  G  G  Q     
              E  E  C  C  N  _  N  N  N  1  Q  
              D  N  P  C  D  L  D  D  D  5  9  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
     Q16 |  7                                39 | Q10 
     Q17 |  8                                38 | Q11 
     Q18 |  9                                37 | Q12 
     GND | 10                                36 | Q13 
RESERVED | 11                                35 | VCC 
     Q19 | 12         EPM7032LC44-6          34 | Q14 
RESERVED | 13                                33 | Q4 
     Q20 | 14                                32 | Q8 
     VCC | 15                                31 | Q7 
     Q21 | 16                                30 | GND 
     Q22 | 17                                29 | Q0 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              Q  R  R  R  G  V  Q  Q  Q  Q  Q  
              2  E  E  E  N  C  6  1  2  3  5  
              3  S  S  S  D  C                 
                 E  E  E                       
                 R  R  R                       
                 V  V  V                       
                 E  E  E                       
                 D  D  D                       


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:d:\luogical  experiment\the 8st\pinlvji\jishuqi.rpt
jishuqi

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     8/16( 50%)  10/16( 62%)   0/16(  0%)   9/36( 25%) 
B:    LC17 - LC32    16/16(100%)  16/16(100%)   0/16(  0%)  18/36( 50%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            26/32     ( 81%)
Total logic cells used:                         24/32     ( 75%)
Total shareable expanders used:                  0/32     (  0%)
Total Turbo logic cells used:                   24/32     ( 75%)
Total shareable expanders not available (n/a):   0/32     (  0%)
Average fan-in:                                  5.91
Total fan-in:                                   142

Total input pins required:                       3
Total output pins required:                     24
Total bidirectional pins required:               0
Total logic cells required:                     24
Total flipflops required:                       24
Total product terms required:                   78
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:d:\luogical  experiment\the 8st\pinlvji\jishuqi.rpt
jishuqi

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   1      -   -       INPUT  G            0      0   0    0    0    0    0  CLR_L
   4    (1)  (A)      INPUT               0      0   0    0    0    4    0  CP
   5    (2)  (A)      INPUT               0      0   0    0    0    4    0  EN


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:d:\luogical  experiment\the 8st\pinlvji\jishuqi.rpt
jishuqi

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  29     27    B         FF      t        0      0   0    2    4    4    0  Q0 (|09jishuqi:4|:15)
  25     31    B         FF      t        0      0   0    2    3    4    0  Q1 (|09jishuqi:4|:14)
  26     30    B         FF      t        0      0   0    2    4    3    0  Q2 (|09jishuqi:4|:13)
  27     29    B         FF      t        0      0   0    2    4    8    0  Q3 (|09jishuqi:4|:12)
  33     24    B         FF      t        0      0   0    0    5    4    0  Q4 (|09jishuqi:6|:15)
  28     28    B         FF      t        0      0   0    0    4    4    0  Q5 (|09jishuqi:6|:14)
  24     32    B         FF      t        0      0   0    0    5    3    0  Q6 (|09jishuqi:6|:13)
  31     26    B         FF      t        0      0   0    0    5    8    0  Q7 (|09jishuqi:6|:12)
  32     25    B         FF      t        0      0   0    0    5    4    0  Q8 (|09jishuqi:5|:15)
  40     18    B         FF      t        0      0   0    0    4    4    0  Q9 (|09jishuqi:5|:14)
  39     19    B         FF      t        0      0   0    0    5    3    0  Q10 (|09jishuqi:5|:13)
  38     20    B         FF      t        0      0   0    0    5    8    0  Q11 (|09jishuqi:5|:12)
  37     21    B         FF      t        0      0   0    0    5    4    0  Q12 (|09jishuqi:9|:15)
  36     22    B         FF      t        0      0   0    0    4    4    0  Q13 (|09jishuqi:9|:14)
  34     23    B         FF      t        0      0   0    0    5    3    0  Q14 (|09jishuqi:9|:13)
  41     17    B         FF      t        0      0   0    0    5    8    0  Q15 (|09jishuqi:9|:12)
   7      4    A         FF      t        0      0   0    0    5    4    0  Q16 (|09jishuqi:7|:15)
   8      5    A         FF      t        0      0   0    0    4    4    0  Q17 (|09jishuqi:7|:14)
   9      6    A         FF      t        0      0   0    0    5    3    0  Q18 (|09jishuqi:7|:13)
  12      8    A         FF      t        0      0   0    0    5    8    0  Q19 (|09jishuqi:7|:12)
  14     10    A         FF      t        0      0   0    0    5    4    0  Q20 (|09jishuqi:8|:15)
  16     11    A         FF      t        0      0   0    0    4    4    0  Q21 (|09jishuqi:8|:14)
  17     12    A         FF      t        0      0   0    0    5    3    0  Q22 (|09jishuqi:8|:13)
  18     13    A         FF      t        0      0   0    0    5    4    0  Q23 (|09jishuqi:8|:12)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:d:\luogical  experiment\the 8st\pinlvji\jishuqi.rpt
jishuqi

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                         Logic cells placed in LAB 'A'
        +--------------- LC4 Q16
        | +------------- LC5 Q17
        | | +----------- LC6 Q18
        | | | +--------- LC8 Q19
        | | | | +------- LC10 Q20
        | | | | | +----- LC11 Q21
        | | | | | | +--- LC12 Q22
        | | | | | | | +- LC13 Q23
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'A':