📄 acc.rpt
字号:
# _LC102 & _X016 & _X018
# i11 & o11;
_X018 = EXP(!i11 & !o11);
_X016 = EXP(!i10 & !o10);
-- Node name is 'o13' = 'count13' from file "acc.tdf" line 7, column 6
-- Equation name is 'o13', location is LC104, type is output.
o13 = DFFE( _EQ021 $ _LC108, GLOBAL( Clk), VCC, VCC, VCC);
_EQ021 = _X020 & _X021;
_X020 = EXP(!i13 & !o13);
_X021 = EXP( i13 & o13);
-- Node name is 'o14' = 'count14' from file "acc.tdf" line 7, column 6
-- Equation name is 'o14', location is LC107, type is output.
o14 = DFFE( _EQ022 $ _EQ023, GLOBAL( Clk), VCC, VCC, VCC);
_EQ022 = i13 & o13
# _LC108 & _X020;
_X020 = EXP(!i13 & !o13);
_EQ023 = _X022 & _X023;
_X022 = EXP(!i14 & !o14);
_X023 = EXP( i14 & o14);
-- Node name is 'o15' = 'count15' from file "acc.tdf" line 7, column 6
-- Equation name is 'o15', location is LC105, type is output.
o15 = DFFE( _EQ024 $ !_LC112, GLOBAL( Clk), VCC, VCC, VCC);
_EQ024 = i13 & o13 & _X022
# _LC108 & _X020 & _X022
# i14 & o14;
_X022 = EXP(!i14 & !o14);
_X020 = EXP(!i13 & !o13);
-- Node name is 'o16' = 'count16' from file "acc.tdf" line 7, column 6
-- Equation name is 'o16', location is LC118, type is output.
o16 = DFFE( _EQ025 $ _LC103, GLOBAL( Clk), VCC, VCC, VCC);
_EQ025 = _X024 & _X025;
_X024 = EXP(!i16 & !o16);
_X025 = EXP( i16 & o16);
-- Node name is 'o17' = 'count17' from file "acc.tdf" line 7, column 6
-- Equation name is 'o17', location is LC123, type is output.
o17 = DFFE( _EQ026 $ _EQ027, GLOBAL( Clk), VCC, VCC, VCC);
_EQ026 = i16 & o16
# _LC103 & _X024;
_X024 = EXP(!i16 & !o16);
_EQ027 = _X026 & _X027;
_X026 = EXP(!i17 & !o17);
_X027 = EXP( i17 & o17);
-- Node name is 'o18' = 'count18' from file "acc.tdf" line 7, column 6
-- Equation name is 'o18', location is LC115, type is output.
o18 = DFFE( _EQ028 $ !_LC114, GLOBAL( Clk), VCC, VCC, VCC);
_EQ028 = i16 & o16 & _X026
# _LC103 & _X024 & _X026
# i17 & o17;
_X026 = EXP(!i17 & !o17);
_X024 = EXP(!i16 & !o16);
-- Node name is 'o19' = 'count19' from file "acc.tdf" line 7, column 6
-- Equation name is 'o19', location is LC091, type is output.
o19 = DFFE( _EQ029 $ _LC122, GLOBAL( Clk), VCC, VCC, VCC);
_EQ029 = _X028 & _X029;
_X028 = EXP(!i19 & !o19);
_X029 = EXP( i19 & o19);
-- Node name is 'o20' = 'count20' from file "acc.tdf" line 7, column 6
-- Equation name is 'o20', location is LC094, type is output.
o20 = DFFE( _EQ030 $ _EQ031, GLOBAL( Clk), VCC, VCC, VCC);
_EQ030 = i19 & o19
# _LC122 & _X028;
_X028 = EXP(!i19 & !o19);
_EQ031 = _X030 & _X031;
_X030 = EXP(!i20 & !o20);
_X031 = EXP( i20 & o20);
-- Node name is 'o21' = 'count21' from file "acc.tdf" line 7, column 6
-- Equation name is 'o21', location is LC093, type is output.
o21 = DFFE( _EQ032 $ !_LC083, GLOBAL( Clk), VCC, VCC, VCC);
_EQ032 = i19 & o19 & _X030
# _LC122 & _X028 & _X030
# i20 & o20;
_X030 = EXP(!i20 & !o20);
_X028 = EXP(!i19 & !o19);
-- Node name is 'o22' = 'count22' from file "acc.tdf" line 7, column 6
-- Equation name is 'o22', location is LC075, type is output.
o22 = DFFE( _EQ033 $ _LC081, GLOBAL( Clk), VCC, VCC, VCC);
_EQ033 = _X032 & _X033;
_X032 = EXP(!i22 & !o22);
_X033 = EXP( i22 & o22);
-- Node name is 'o23' = 'count23' from file "acc.tdf" line 7, column 6
-- Equation name is 'o23', location is LC073, type is output.
o23 = DFFE( _EQ034 $ _EQ035, GLOBAL( Clk), VCC, VCC, VCC);
_EQ034 = i22 & o22
# _LC081 & _X032;
_X032 = EXP(!i22 & !o22);
_EQ035 = _X034 & _X035;
_X034 = EXP(!i23 & !o23);
_X035 = EXP( i23 & o23);
-- Node name is '~136~1' from file "acc.tdf" line 10, column 21
-- Equation name is '~136~1', location is LC121, type is buried.
-- synthesized logic cell
_LC121 = LCELL( _EQ036 $ GND);
_EQ036 = i3 & o3
# !i3 & !o3;
-- Node name is ':137' from file "acc.tdf" line 10, column 21
-- Equation name is '_LC124', type is buried
_LC124 = LCELL( _EQ037 $ _EQ038);
_EQ037 = i0 & !_LC121 & o0 & _X002 & _X004
# i1 & !_LC121 & o1 & _X004
# i2 & !_LC121 & o2;
_X002 = EXP(!i1 & !o1);
_X004 = EXP(!i2 & !o2);
_EQ038 = i3 & o3;
-- Node name is ':168' from file "acc.tdf" line 10, column 21
-- Equation name is '_LC113', type is buried
_LC113 = LCELL( _EQ039 $ _EQ040);
_EQ039 = i4 & o4 & _X008 & _X010 & _X011
# _LC124 & _X006 & _X008 & _X010 & _X011
# i5 & o5 & _X010 & _X011;
_X008 = EXP(!i5 & !o5);
_X010 = EXP(!i6 & !o6);
_X011 = EXP( i6 & o6);
_X006 = EXP(!i4 & !o4);
_EQ040 = i6 & o6;
-- Node name is '~198~1' from file "acc.tdf" line 10, column 21
-- Equation name is '~198~1', location is LC100, type is buried.
-- synthesized logic cell
_LC100 = LCELL( _EQ041 $ GND);
_EQ041 = i9 & o9
# !i9 & !o9;
-- Node name is ':199' from file "acc.tdf" line 10, column 21
-- Equation name is '_LC102', type is buried
_LC102 = LCELL( _EQ042 $ _EQ043);
_EQ042 = i7 & !_LC100 & o7 & _X014
# !_LC100 & _LC113 & _X012 & _X014
# i8 & !_LC100 & o8;
_X014 = EXP(!i8 & !o8);
_X012 = EXP(!i7 & !o7);
_EQ043 = i9 & o9;
-- Node name is '~229~1' from file "acc.tdf" line 10, column 21
-- Equation name is '~229~1', location is LC098, type is buried.
-- synthesized logic cell
_LC098 = LCELL( _EQ044 $ GND);
_EQ044 = i12 & o12
# !i12 & !o12;
-- Node name is ':230' from file "acc.tdf" line 10, column 21
-- Equation name is '_LC108', type is buried
_LC108 = LCELL( _EQ045 $ _EQ046);
_EQ045 = i10 & !_LC098 & o10 & _X018
# !_LC098 & _LC102 & _X016 & _X018
# i11 & !_LC098 & o11;
_X018 = EXP(!i11 & !o11);
_X016 = EXP(!i10 & !o10);
_EQ046 = i12 & o12;
-- Node name is '~260~1' from file "acc.tdf" line 10, column 21
-- Equation name is '~260~1', location is LC112, type is buried.
-- synthesized logic cell
_LC112 = LCELL( _EQ047 $ GND);
_EQ047 = i15 & o15
# !i15 & !o15;
-- Node name is ':261' from file "acc.tdf" line 10, column 21
-- Equation name is '_LC103', type is buried
_LC103 = LCELL( _EQ048 $ _EQ049);
_EQ048 = i13 & !_LC112 & o13 & _X022
# _LC108 & !_LC112 & _X020 & _X022
# i14 & !_LC112 & o14;
_X022 = EXP(!i14 & !o14);
_X020 = EXP(!i13 & !o13);
_EQ049 = i15 & o15;
-- Node name is '~291~1' from file "acc.tdf" line 10, column 21
-- Equation name is '~291~1', location is LC114, type is buried.
-- synthesized logic cell
_LC114 = LCELL( _EQ050 $ GND);
_EQ050 = i18 & o18
# !i18 & !o18;
-- Node name is ':292' from file "acc.tdf" line 10, column 21
-- Equation name is '_LC122', type is buried
_LC122 = LCELL( _EQ051 $ _EQ052);
_EQ051 = i16 & !_LC114 & o16 & _X026
# _LC103 & !_LC114 & _X024 & _X026
# i17 & !_LC114 & o17;
_X026 = EXP(!i17 & !o17);
_X024 = EXP(!i16 & !o16);
_EQ052 = i18 & o18;
-- Node name is '~322~1' from file "acc.tdf" line 10, column 21
-- Equation name is '~322~1', location is LC083, type is buried.
-- synthesized logic cell
_LC083 = LCELL( _EQ053 $ GND);
_EQ053 = i21 & o21
# !i21 & !o21;
-- Node name is ':323' from file "acc.tdf" line 10, column 21
-- Equation name is '_LC081', type is buried
_LC081 = LCELL( _EQ054 $ _EQ055);
_EQ054 = i19 & !_LC083 & o19 & _X030
# !_LC083 & _LC122 & _X028 & _X030
# i20 & !_LC083 & o20;
_X030 = EXP(!i20 & !o20);
_X028 = EXP(!i19 & !o19);
_EQ055 = i21 & o21;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X002 occurs in LABs F, H
-- _X012 occurs in LABs E, G
-- _X016 occurs in LABs F, G
Project Information g:\max2work\ddsman\acc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,280K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -