📄 acc.rpt
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Pin
83 -> - - - | - - - - - - - - | <-- Clk
12 -> * - - | - - - - * - * - | <-- i7
18 -> - * * | - - - - * - - - | <-- i22
17 -> - - * | - - - - * - - - | <-- i23
LC113-> * - - | - - - - * - * - | <-- :168
LC81 -> - * * | - - - - * - - - | <-- :323
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\max2work\ddsman\acc.rpt
acc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--------------- LC88 o0
| +------------- LC85 o1
| | +----------- LC86 o10
| | | +--------- LC91 o19
| | | | +------- LC94 o20
| | | | | +----- LC93 o21
| | | | | | +--- LC83 ~322~1
| | | | | | | +- LC81 :323
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'F'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC88 -> * * - - - - - - | - - - - - * - * | <-- o0
LC85 -> - * - - - - - - | - - - - - * - * | <-- o1
LC86 -> - - * - - - - - | - - - - - * * - | <-- o10
LC91 -> - - - * * * - * | - - - - - * - - | <-- o19
LC94 -> - - - - * * - * | - - - - - * - - | <-- o20
LC93 -> - - - - - - * * | - - - - - * - - | <-- o21
LC83 -> - - - - - * - * | - - - - - * - - | <-- ~322~1
Pin
83 -> - - - - - - - - | - - - - - - - - | <-- Clk
9 -> * * - - - - - - | - - - - - * - * | <-- i0
10 -> - * - - - - - - | - - - - - * - * | <-- i1
11 -> - - * - - - - - | - - - - - * * - | <-- i10
4 -> - - - * * * - * | - - - - - * - - | <-- i19
21 -> - - - - * * - * | - - - - - * - - | <-- i20
20 -> - - - - - - * * | - - - - - * - - | <-- i21
LC102-> - - * - - - - - | - - - - - * * - | <-- :199
LC122-> - - - * * * - * | - - - - - * - - | <-- :292
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\max2work\ddsman\acc.rpt
acc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------------------- LC99 o8
| +----------------------- LC109 o9
| | +--------------------- LC97 o11
| | | +------------------- LC101 o12
| | | | +----------------- LC104 o13
| | | | | +--------------- LC107 o14
| | | | | | +------------- LC105 o15
| | | | | | | +----------- LC100 ~198~1
| | | | | | | | +--------- LC102 :199
| | | | | | | | | +------- LC98 ~229~1
| | | | | | | | | | +----- LC108 :230
| | | | | | | | | | | +--- LC112 ~260~1
| | | | | | | | | | | | +- LC103 :261
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC99 -> * * - - - - - - * - - - - | - - - - - - * - | <-- o8
LC109-> - - - - - - - * * - - - - | - - - - - - * - | <-- o9
LC97 -> - - * * - - - - - - * - - | - - - - - - * - | <-- o11
LC101-> - - - - - - - - - * * - - | - - - - - - * - | <-- o12
LC104-> - - - - * * * - - - - - * | - - - - - - * - | <-- o13
LC107-> - - - - - * * - - - - - * | - - - - - - * - | <-- o14
LC105-> - - - - - - - - - - - * * | - - - - - - * - | <-- o15
LC100-> - * - - - - - - * - - - - | - - - - - - * - | <-- ~198~1
LC102-> - - * * - - - - - - * - - | - - - - - * * - | <-- :199
LC98 -> - - - * - - - - - - * - - | - - - - - - * - | <-- ~229~1
LC108-> - - - - * * * - - - - - * | - - - - - - * - | <-- :230
LC112-> - - - - - - * - - - - - * | - - - - - - * - | <-- ~260~1
Pin
83 -> - - - - - - - - - - - - - | - - - - - - - - | <-- Clk
12 -> * * - - - - - - * - - - - | - - - - * - * - | <-- i7
37 -> * * - - - - - - * - - - - | - - - - - - * - | <-- i8
54 -> - - - - - - - * * - - - - | - - - - - - * - | <-- i9
11 -> - - * * - - - - - - * - - | - - - - - * * - | <-- i10
52 -> - - * * - - - - - - * - - | - - - - - - * - | <-- i11
48 -> - - - - - - - - - * * - - | - - - - - - * - | <-- i12
33 -> - - - - * * * - - - - - * | - - - - - - * - | <-- i13
15 -> - - - - - * * - - - - - * | - - - - - - * - | <-- i14
16 -> - - - - - - - - - - - * * | - - - - - - * - | <-- i15
LC65 -> * * - - - - - - * - - - - | - - - - * - * - | <-- o7
LC86 -> - - * * - - - - - - * - - | - - - - - * * - | <-- o10
LC113-> * * - - - - - - * - - - - | - - - - * - * - | <-- :168
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\max2work\ddsman\acc.rpt
acc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------- LC117 o2
| +----------------------- LC120 o3
| | +--------------------- LC125 o4
| | | +------------------- LC126 o5
| | | | +----------------- LC128 o6
| | | | | +--------------- LC118 o16
| | | | | | +------------- LC123 o17
| | | | | | | +----------- LC115 o18
| | | | | | | | +--------- LC121 ~136~1
| | | | | | | | | +------- LC124 :137
| | | | | | | | | | +----- LC113 :168
| | | | | | | | | | | +--- LC114 ~291~1
| | | | | | | | | | | | +- LC122 :292
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC117-> * * - - - - - - - * - - - | - - - - - - - * | <-- o2
LC120-> - - - - - - - - * * - - - | - - - - - - - * | <-- o3
LC125-> - - * * * - - - - - * - - | - - - - - - - * | <-- o4
LC126-> - - - * * - - - - - * - - | - - - - - - - * | <-- o5
LC128-> - - - - * - - - - - * - - | - - - - - - - * | <-- o6
LC118-> - - - - - * * * - - - - * | - - - - - - - * | <-- o16
LC123-> - - - - - - * * - - - - * | - - - - - - - * | <-- o17
LC115-> - - - - - - - - - - - * * | - - - - - - - * | <-- o18
LC121-> - * - - - - - - - * - - - | - - - - - - - * | <-- ~136~1
LC124-> - - * * * - - - - - * - - | - - - - - - - * | <-- :137
LC114-> - - - - - - - * - - - - * | - - - - - - - * | <-- ~291~1
Pin
83 -> - - - - - - - - - - - - - | - - - - - - - - | <-- Clk
9 -> * * - - - - - - - * - - - | - - - - - * - * | <-- i0
10 -> * * - - - - - - - * - - - | - - - - - * - * | <-- i1
31 -> * * - - - - - - - * - - - | - - - - - - - * | <-- i2
34 -> - - - - - - - - * * - - - | - - - - - - - * | <-- i3
29 -> - - * * * - - - - - * - - | - - - - - - - * | <-- i4
27 -> - - - * * - - - - - * - - | - - - - - - - * | <-- i5
41 -> - - - - * - - - - - * - - | - - - - - - - * | <-- i6
8 -> - - - - - * * * - - - - * | - - - - - - - * | <-- i16
6 -> - - - - - - * * - - - - * | - - - - - - - * | <-- i17
5 -> - - - - - - - - - - - * * | - - - - - - - * | <-- i18
LC88 -> * * - - - - - - - * - - - | - - - - - * - * | <-- o0
LC85 -> * * - - - - - - - * - - - | - - - - - * - * | <-- o1
LC103-> - - - - - * * * - - - - * | - - - - - - - * | <-- :261
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\max2work\ddsman\acc.rpt
acc
** EQUATIONS **
Clk : INPUT;
i0 : INPUT;
i1 : INPUT;
i2 : INPUT;
i3 : INPUT;
i4 : INPUT;
i5 : INPUT;
i6 : INPUT;
i7 : INPUT;
i8 : INPUT;
i9 : INPUT;
i10 : INPUT;
i11 : INPUT;
i12 : INPUT;
i13 : INPUT;
i14 : INPUT;
i15 : INPUT;
i16 : INPUT;
i17 : INPUT;
i18 : INPUT;
i19 : INPUT;
i20 : INPUT;
i21 : INPUT;
i22 : INPUT;
i23 : INPUT;
-- Node name is 'o0' = 'count0' from file "acc.tdf" line 7, column 6
-- Equation name is 'o0', location is LC088, type is output.
o0 = DFFE( _EQ001 $ _EQ002, GLOBAL( Clk), VCC, VCC, VCC);
_EQ001 = !i0 & !o0 & _X001;
_X001 = EXP( i0 & o0);
_EQ002 = _X001;
_X001 = EXP( i0 & o0);
-- Node name is 'o1' = 'count1' from file "acc.tdf" line 7, column 6
-- Equation name is 'o1', location is LC085, type is output.
o1 = DFFE( _EQ003 $ _EQ004, GLOBAL( Clk), VCC, VCC, VCC);
_EQ003 = _X002 & _X003;
_X002 = EXP(!i1 & !o1);
_X003 = EXP( i1 & o1);
_EQ004 = i0 & o0;
-- Node name is 'o2' = 'count2' from file "acc.tdf" line 7, column 6
-- Equation name is 'o2', location is LC117, type is output.
o2 = DFFE( _EQ005 $ _EQ006, GLOBAL( Clk), VCC, VCC, VCC);
_EQ005 = i0 & o0 & _X002
# i1 & o1;
_X002 = EXP(!i1 & !o1);
_EQ006 = _X004 & _X005;
_X004 = EXP(!i2 & !o2);
_X005 = EXP( i2 & o2);
-- Node name is 'o3' = 'count3' from file "acc.tdf" line 7, column 6
-- Equation name is 'o3', location is LC120, type is output.
o3 = DFFE( _EQ007 $ !_LC121, GLOBAL( Clk), VCC, VCC, VCC);
_EQ007 = i0 & o0 & _X002 & _X004
# i1 & o1 & _X004
# i2 & o2;
_X002 = EXP(!i1 & !o1);
_X004 = EXP(!i2 & !o2);
-- Node name is 'o4' = 'count4' from file "acc.tdf" line 7, column 6
-- Equation name is 'o4', location is LC125, type is output.
o4 = DFFE( _EQ008 $ _LC124, GLOBAL( Clk), VCC, VCC, VCC);
_EQ008 = _X006 & _X007;
_X006 = EXP(!i4 & !o4);
_X007 = EXP( i4 & o4);
-- Node name is 'o5' = 'count5' from file "acc.tdf" line 7, column 6
-- Equation name is 'o5', location is LC126, type is output.
o5 = DFFE( _EQ009 $ _EQ010, GLOBAL( Clk), VCC, VCC, VCC);
_EQ009 = i4 & o4
# _LC124 & _X006;
_X006 = EXP(!i4 & !o4);
_EQ010 = _X008 & _X009;
_X008 = EXP(!i5 & !o5);
_X009 = EXP( i5 & o5);
-- Node name is 'o6' = 'count6' from file "acc.tdf" line 7, column 6
-- Equation name is 'o6', location is LC128, type is output.
o6 = DFFE( _EQ011 $ _EQ012, GLOBAL( Clk), VCC, VCC, VCC);
_EQ011 = i4 & o4 & _X008
# _LC124 & _X006 & _X008
# i5 & o5;
_X008 = EXP(!i5 & !o5);
_X006 = EXP(!i4 & !o4);
_EQ012 = _X010 & _X011;
_X010 = EXP(!i6 & !o6);
_X011 = EXP( i6 & o6);
-- Node name is 'o7' = 'count7' from file "acc.tdf" line 7, column 6
-- Equation name is 'o7', location is LC065, type is output.
o7 = DFFE( _EQ013 $ _LC113, GLOBAL( Clk), VCC, VCC, VCC);
_EQ013 = _X012 & _X013;
_X012 = EXP(!i7 & !o7);
_X013 = EXP( i7 & o7);
-- Node name is 'o8' = 'count8' from file "acc.tdf" line 7, column 6
-- Equation name is 'o8', location is LC099, type is output.
o8 = DFFE( _EQ014 $ _EQ015, GLOBAL( Clk), VCC, VCC, VCC);
_EQ014 = i7 & o7
# _LC113 & _X012;
_X012 = EXP(!i7 & !o7);
_EQ015 = _X014 & _X015;
_X014 = EXP(!i8 & !o8);
_X015 = EXP( i8 & o8);
-- Node name is 'o9' = 'count9' from file "acc.tdf" line 7, column 6
-- Equation name is 'o9', location is LC109, type is output.
o9 = DFFE( _EQ016 $ !_LC100, GLOBAL( Clk), VCC, VCC, VCC);
_EQ016 = i7 & o7 & _X014
# _LC113 & _X012 & _X014
# i8 & o8;
_X014 = EXP(!i8 & !o8);
_X012 = EXP(!i7 & !o7);
-- Node name is 'o10' = 'count10' from file "acc.tdf" line 7, column 6
-- Equation name is 'o10', location is LC086, type is output.
o10 = DFFE( _EQ017 $ _LC102, GLOBAL( Clk), VCC, VCC, VCC);
_EQ017 = _X016 & _X017;
_X016 = EXP(!i10 & !o10);
_X017 = EXP( i10 & o10);
-- Node name is 'o11' = 'count11' from file "acc.tdf" line 7, column 6
-- Equation name is 'o11', location is LC097, type is output.
o11 = DFFE( _EQ018 $ _EQ019, GLOBAL( Clk), VCC, VCC, VCC);
_EQ018 = i10 & o10
# _LC102 & _X016;
_X016 = EXP(!i10 & !o10);
_EQ019 = _X018 & _X019;
_X018 = EXP(!i11 & !o11);
_X019 = EXP( i11 & o11);
-- Node name is 'o12' = 'count12' from file "acc.tdf" line 7, column 6
-- Equation name is 'o12', location is LC101, type is output.
o12 = DFFE( _EQ020 $ !_LC098, GLOBAL( Clk), VCC, VCC, VCC);
_EQ020 = i10 & o10 & _X018
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