📄 reg24bit.rpt
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Pin
83 -> - - - - - - - | - - - - - - - - | <-- Clk
11 -> * * * * * * * | - - - - * * * * | <-- Clrn
10 -> * - - - - - - | - - - - - * - - | <-- D15
9 -> - * - - - - - | - - - - - * - - | <-- D16
8 -> - - * - - - - | - - - - - * - - | <-- D17
6 -> - - - * - - - | - - - - - * - - | <-- D18
5 -> - - - - * - - | - - - - - * - - | <-- D19
4 -> - - - - - * - | - - - - - * - - | <-- D20
21 -> - - - - - - * | - - - - - * - - | <-- D21
12 -> * * * * * * * | - - - - * * * * | <-- Enable
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\max2work\ddsman\reg24bit.rpt
reg24bit
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------- LC109 Q8
| +----------- LC107 Q9
| | +--------- LC105 Q10
| | | +------- LC97 Q11
| | | | +----- LC99 Q12
| | | | | +--- LC101 Q13
| | | | | | +- LC104 Q14
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'G'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
83 -> - - - - - - - | - - - - - - - - | <-- Clk
11 -> * * * * * * * | - - - - * * * * | <-- Clrn
48 -> * - - - - - - | - - - - - - * - | <-- D8
52 -> - * - - - - - | - - - - - - * - | <-- D9
28 -> - - * - - - - | - - - - - - * - | <-- D10
22 -> - - - * - - - | - - - - - - * - | <-- D11
30 -> - - - - * - - | - - - - - - * - | <-- D12
16 -> - - - - - * - | - - - - - - * - | <-- D13
17 -> - - - - - - * | - - - - - - * - | <-- D14
12 -> * * * * * * * | - - - - * * * * | <-- Enable
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\max2work\ddsman\reg24bit.rpt
reg24bit
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+--------------- LC128 Q0
| +------------- LC125 Q1
| | +----------- LC117 Q2
| | | +--------- LC118 Q3
| | | | +------- LC126 Q4
| | | | | +----- LC123 Q5
| | | | | | +--- LC115 Q6
| | | | | | | +- LC120 Q7
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'H'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
83 -> - - - - - - - - | - - - - - - - - | <-- Clk
11 -> * * * * * * * * | - - - - * * * * | <-- Clrn
29 -> * - - - - - - - | - - - - - - - * | <-- D0
31 -> - * - - - - - - | - - - - - - - * | <-- D1
15 -> - - * - - - - - | - - - - - - - * | <-- D2
27 -> - - - * - - - - | - - - - - - - * | <-- D3
41 -> - - - - * - - - | - - - - - - - * | <-- D4
37 -> - - - - - * - - | - - - - - - - * | <-- D5
34 -> - - - - - - * - | - - - - - - - * | <-- D6
33 -> - - - - - - - * | - - - - - - - * | <-- D7
12 -> * * * * * * * * | - - - - * * * * | <-- Enable
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\max2work\ddsman\reg24bit.rpt
reg24bit
** EQUATIONS **
Clk : INPUT;
Clrn : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
D8 : INPUT;
D9 : INPUT;
D10 : INPUT;
D11 : INPUT;
D12 : INPUT;
D13 : INPUT;
D14 : INPUT;
D15 : INPUT;
D16 : INPUT;
D17 : INPUT;
D18 : INPUT;
D19 : INPUT;
D20 : INPUT;
D21 : INPUT;
D22 : INPUT;
D23 : INPUT;
Enable : INPUT;
-- Node name is 'Q0' = '|LPM_FF:r|dffs0' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q0', type is output
Q0 = DFFE( D0 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q1' = '|LPM_FF:r|dffs1' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q1', type is output
Q1 = DFFE( D1 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q2' = '|LPM_FF:r|dffs2' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q2', type is output
Q2 = DFFE( D2 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q3' = '|LPM_FF:r|dffs3' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q3', type is output
Q3 = DFFE( D3 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q4' = '|LPM_FF:r|dffs4' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q4', type is output
Q4 = DFFE( D4 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q5' = '|LPM_FF:r|dffs5' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q5', type is output
Q5 = DFFE( D5 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q6' = '|LPM_FF:r|dffs6' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q6', type is output
Q6 = DFFE( D6 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q7' = '|LPM_FF:r|dffs7' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q7', type is output
Q7 = DFFE( D7 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q8' = '|LPM_FF:r|dffs8' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q8', type is output
Q8 = DFFE( D8 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q9' = '|LPM_FF:r|dffs9' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q9', type is output
Q9 = DFFE( D9 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q10' = '|LPM_FF:r|dffs10' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q10', type is output
Q10 = DFFE( D10 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q11' = '|LPM_FF:r|dffs11' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q11', type is output
Q11 = DFFE( D11 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q12' = '|LPM_FF:r|dffs12' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q12', type is output
Q12 = DFFE( D12 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q13' = '|LPM_FF:r|dffs13' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q13', type is output
Q13 = DFFE( D13 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q14' = '|LPM_FF:r|dffs14' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q14', type is output
Q14 = DFFE( D14 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q15' = '|LPM_FF:r|dffs15' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q15', type is output
Q15 = DFFE( D15 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q16' = '|LPM_FF:r|dffs16' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q16', type is output
Q16 = DFFE( D16 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q17' = '|LPM_FF:r|dffs17' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q17', type is output
Q17 = DFFE( D17 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q18' = '|LPM_FF:r|dffs18' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q18', type is output
Q18 = DFFE( D18 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q19' = '|LPM_FF:r|dffs19' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q19', type is output
Q19 = DFFE( D19 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q20' = '|LPM_FF:r|dffs20' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q20', type is output
Q20 = DFFE( D20 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q21' = '|LPM_FF:r|dffs21' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q21', type is output
Q21 = DFFE( D21 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q22' = '|LPM_FF:r|dffs22' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q22', type is output
Q22 = DFFE( D22 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Node name is 'Q23' = '|LPM_FF:r|dffs23' from file "lpm_ff.tdf" line 58, column 6
-- Equation name is 'Q23', type is output
Q23 = DFFE( D23 $ GND, GLOBAL( Clk), !Clrn, VCC, Enable);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information g:\max2work\ddsman\reg24bit.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,287K
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