reg24bit.vhd

来自「自己使用VHDL语言编写的24位寄存器.主要用于DDS中」· VHDL 代码 · 共 19 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY reg24bit IS
		PORT(D			:IN		STD_LOGIC_VECTOR(23 DOWNTO 0);
			 Clk,Clrn,Enable	:IN		STD_LOGIC;
			 Q			:OUT	STD_LOGIC_VECTOR(23 DOWNTO 0)
			);
END reg24bit;
ARCHITECTURE a OF reg24bit IS
BEGIN
	r: lpm_ff
		GENERIC MAP(LPM_WIDTH => 24)
		PORT MAP (DATA => D, ENABLE=>Enable, CLOCK =>Clk, ACLR =>Clrn, Q => Q);
END a;