cpu0.ptf

低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码

SYSTEM cpu0
{
   System_Wizard_Version = "7.00";
   System_Wizard_Build = "33";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "CYCLONE";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "1";
      do_build_sim = "1";
      hardcopy_compatible = "0";
      board_class = "";
      CLOCKS 
      {
         CLOCK clk
         {
            frequency = "50000000";
            source = "External";
            display_name = "clk";
            Is_Clock_Source = "0";
         }
         CLOCK pll_0_c0
         {
            frequency = "2048000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from pll_0";
            pipeline = "0";
         }
         CLOCK clk_1
         {
            frequency = "2048000";
            source = "pll_0_c0";
            Is_Clock_Source = "0";
            display_name = "clk_1";
            pipeline = "0";
         }
      }
      hdl_language = "vhdl";
      device_family_id = "CYCLONE";
      view_master_columns = "1";
      view_master_priorities = "0";
      name_column_width = "75";
      desc_column_width = "75";
      bustype_column_width = "0";
      base_column_width = "75";
      clock_column_width = "80";
      end_column_width = "75";
      view_frame_window = "128:100:1024:600";
   }
   MODULE onchip_memory_0
   {
      class = "altera_avalon_onchip_memory2";
      class_version = "7.0";
      iss_model_name = "altera_memory";
      HDL_INFO 
      {
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         allow_mram_sim_contents_only_file = "0";
         ram_block_type = "M4K";
         init_contents_file = "onchip_memory_0";
         non_default_init_file_enabled = "0";
         gui_ram_block_type = "Automatic";
         Writeable = "0";
         dual_port = "0";
         Size_Value = "4";
         Size_Multiple = "1024";
      }
      SYSTEM_BUILDER_INFO 
      {
         Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "onchip_memory";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Memory_Device = "1";
            Address_Group = "0";
            Address_Alignment = "dynamic";
            Address_Width = "10";
            Data_Width = "32";
            Has_IRQ = "0";
            Read_Wait_States = "0";
            Write_Wait_States = "0";
            Address_Span = "4096";
            Read_Latency = "1";
            Is_Channel = "1";
            Is_Writable = "0";
         }
      }
      SLAVE s2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Memory_Device = "1";
            Address_Group = "0";
            Address_Alignment = "dynamic";
            Address_Width = "10";
            Data_Width = "32";
            Has_IRQ = "0";
            Read_Wait_States = "0";
            Write_Wait_States = "0";
            Address_Span = "4096";
            Read_Latency = "1";
            Is_Channel = "1";
            Is_Enabled = "0";
            Is_Writable = "0";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "chipselect";
               conditional = "1";
            }
            SIGNAL b
            {
               name = "write";
               conditional = "1";
            }
            SIGNAL c
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "byteenable";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "writedata";
               radix = "hexadecimal";
               conditional = "1";
            }
         }
      }
   }
   MODULE pll_0
   {
      class = "altera_avalon_pll";
      class_version = "7.0";
      HDL_INFO 
      {
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Default_Module_Name = "pll";
         Clock_Source = "clk";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIII,STRATIXIIGX,CYCLONE,CYCLONEII,CYCLONEIII";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = " Avalon PLL: <br>
         input clock configured: <b>clk</b>
        ";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "0";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Date_Modified = "";
            Is_Enabled = "1";
            Instantiate_In_System_Module = "1";
            Requires_Internal_Clock_Promotion = "Yes";
            Is_Clock_Source = "1";
            Base_Address = "--unknown--";
            Address_Group = "0";
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "0";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         locked = "None";
         areset = "None";
         pllena = "None";
         pfdena = "None";
         Config_Done = "1";
         UI_CONTROL 
         {
            areset_port_exist = "0";
            pllena_port_exist = "0";