ds_fh.fit.summary

来自「扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Sun Jan 13 08:52:31 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : DS_FH
Top-level Entity Name : DS_FH
Family : Cyclone II
Device : EP2C8Q208C7
Timing Models : Final
Total logic elements : 976 / 8,256 ( 12 % )
    Total combinational functions : 719 / 8,256 ( 9 % )
    Dedicated logic registers : 677 / 8,256 ( 8 % )
Total registers : 677
Total pins : 38 / 138 ( 28 % )
Total virtual pins : 0
Total memory bits : 5,120 / 165,888 ( 3 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )