initialization.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;

entity initialization is
port(
	clk1000,clk500,clkx4:in std_logic;
	start:in std_logic;
	initial_hopset:out std_logic_vector(4 downto 0);
	datai_a,dataq_a:out std_logic;
	notready:out std_logic);
end;

architecture one of initialization is
signal nextcount:INTEGER RANGE 0 TO 31;
signal count:INTEGER RANGE 0 TO 15;
signal shift:std_logic_vector(3 downto 0);
signal temp1:std_logic:='0';
signal temp2:std_logic:='0';
begin

process(clkx4,start,nextcount)--初始同步帧
begin
	if start='1' then
		datai_a<='0';dataq_a<='0';
	elsif clkx4'event and clkx4='1' then
		case nextcount is
			when 0 =>datai_a<='0';dataq_a<='1';
			when 1 =>datai_a<='0';dataq_a<='1';
			when 2 =>datai_a<='0';dataq_a<='1';
			when 3 =>datai_a<='0';dataq_a<='1';
			when 4 =>datai_a<='0';dataq_a<='1';
			when 5 =>datai_a<='0';dataq_a<='1';
			when 6 =>datai_a<='0';dataq_a<='1';
			when 7 =>datai_a<='0';dataq_a<='1';
			when 8 =>datai_a<='0';dataq_a<='1';
		--13位巴克码
			when 9 =>datai_a<='1';dataq_a<='1';
			when 10 =>datai_a<='1';dataq_a<='1';
			when 11 =>datai_a<='1';dataq_a<='0';
			when 12 =>datai_a<='0';dataq_a<='1';
			when 13 =>datai_a<='1';dataq_a<='0';
			when 14 =>datai_a<='1';dataq_a<='0';
			when 15 =>datai_a<='1';  
						dataq_a<='1';--帧类型
			when 16 =>datai_a<='1';dataq_a<='1';
		--TOD信息
			when 17 =>datai_a<='0';dataq_a<='1';
			when 18 =>datai_a<='0';dataq_a<='1';
			when 19 =>datai_a<='0';dataq_a<='1';
			when 20 =>datai_a<='0';dataq_a<='1';
			when 21 =>datai_a<='0';dataq_a<='1';
			when 22 =>datai_a<='0';dataq_a<='1';
			when 23 =>datai_a<='0';dataq_a<='1';
			when 24 =>datai_a<='0';dataq_a<='1';
		--信息长度
			when 25 =>datai_a<='0';dataq_a<='0';
			when 26 =>datai_a<='0';dataq_a<='0';
			when 27 =>datai_a<='0';dataq_a<='0';
			when 28 =>datai_a<='1';dataq_a<='0';
			when 29 =>datai_a<='0';dataq_a<='0';
			when 30 =>datai_a<='0';dataq_a<='0';
		--保留位（用于跳频频率转换）
			when 31 =>datai_a<='1';dataq_a<='1';
			when others =>datai_a<='X';dataq_a<='X';	
		end case;
	end if;
end process;

process(start,clkx4)
begin
	if start='1' then
		nextcount<=0;
	elsif clkx4'event and clkx4='1' then
		if nextcount=31 then
			temp1<='1';
		else
			nextcount<=nextcount+1;
		end if;
	end if;
end process;



process(clk1000)--跳频图案初始同步
	variable temp:std_logic;
begin
	if(start='1' or count=32)then
		shift(3 downto 0)<="1111";
		temp:='0';
	elsif(clk1000'event and clk1000='1')then	     
		temp:=shift(1) xor shift(0);----------f(x)=x4+x3+1
		FOR i IN 0 TO 2 LOOP
		    shift(i)<=shift(i+1);
		END LOOP;
	shift(3)<=temp;
	end if;
initial_hopset<='0'&shift;
end process;


PROCESS(start,clk1000)
BEGIN
   IF start='1' THEN
     count<=0;
   ELSIF(clk1000'event AND clk1000='1') THEN
    	IF count=15 THEN
			temp2<='1';
   		ELSE count<=count+1;
  		END IF;
	END IF;
END PROCESS;

process(temp1,temp2)
begin
	if (temp1='1' and temp2='1') then
		notready<='0';
	else
		notready<='1';
	end if;
end process;

end one;