hopset_generator.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity hopset_generator is
   port(
		clk1000:in std_logic;
		notready: in std_logic;
		normal_hopset:out std_logic_vector(4 downto 0)
		);
end hopset_generator;

architecture generator_archi of hopset_generator is
	signal shift:std_logic_vector(30 downto 0);
begin

process(notready,clk1000)
	variable temp:std_logic;
begin
	if(notready='1')then
		shift(30 downto 0)<="1000000000000000000000000000000";
		temp:='0';
	elsif(clk1000'event and clk1000='1')then	     
		temp:=shift(28) xor shift(0);----------x31+x3+1
		FOR i IN 0 TO 29 LOOP
		    shift(i)<=shift(i+1);
		END LOOP;
	shift(30)<=temp;
	end if;
end process;

process(shift)
	variable temp1,temp2:integer range 0 to 31;
begin
	temp1:=conv_integer('0' & shift(30 downto 26));--将shift的数据类型转换为integer类型的数据
	if temp1 >= 20 then--模20运算
		temp2 := temp1-20;
	else temp2 := temp1;
	end if;
	normal_hopset<=conv_std_logic_vector(temp2,5);--将temp2转换为位宽为5的std_logic_vector类型的数据
end process;

end generator_archi;