indata.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity indata is
port(clk:in std_logic;
     notready:in std_logic;
     data:out std_logic);
end;

architecture one of indata is
    signal reg:std_logic_vector(7 downto 0);
begin
process(clk,notready)
begin
if clk'event and clk='1' then
   if notready='1' then
       data<='0';
       reg<="10110101";
   else
       data<=reg(7);
       reg<=reg(6 downto 0)&reg(7);
   end if;
end if;
end process;
end;