m7.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

LIBRARY ieee;       
USE ieee.std_logic_1164.all;    
USE ieee.std_logic_arith.all;

ENTITY M7 IS    ----------x7+x4+x3+x2+1 [2 3 4 7]
PORT(clkx1024:IN STD_LOGIC;
	 notready:IN STD_LOGIC;
	 M_7:OUT STD_LOGIC);
END M7;

ARCHITECTURE generator_archi OF M7 IS 
	SIGNAL count:INTEGER RANGE 0 TO 128;
	SIGNAL enable:STD_LOGIC;

BEGIN



PROCESS(notready,count,clkx1024)
	VARIABLE shift:STD_LOGIC_VECTOR(6 downto 0);
	VARIABLE tmp:STD_LOGIC;
BEGIN
	IF(notready='1'OR count=128) THEN
	  M_7<='0';
	  shift:="1000000";  
	ELSIF(enable='1') THEN
		 IF(clkx1024'event AND clkx1024='1')THEN
		     tmp:=shift(0) XOR shift(3) XOR shift(4)XOR shift(5)XOR (NOT shift(6)and not shift(5)and not shift(4)and not shift(3)and not shift(2)and not shift(1));
		     M_7<=tmp;     
		     FOR i IN 0 TO 5 LOOP
		       shift(i):=shift(i+1);
		     END LOOP;
		     shift(6):=tmp;
		 END IF;
	 END IF;
END PROCESS;

PROCESS(notready,clkx1024)
BEGIN
   IF notready='1' THEN
     count<=0;
   ELSIF(clkx1024'event AND clkx1024='1') THEN
    	IF count=128 THEN
			count<=1;
   		ELSE count<=count+1;
  		END IF;
	END IF;
END PROCESS;

PROCESS(count,clkx1024,notready)
BEGIN
	IF notready='1' THEN
 		 enable<='1';
	elsif(clkx1024'event AND clkx1024='0') THEN
		IF(count=127) THEN
		enable<='0';
		ELSIF(count=128) THEN
		enable<='1';
	    END IF;
	END IF;
END PROCESS;
END generator_archi;