ds_fh.fit.smsg

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Jan 13 08:51:51 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DS_FH -c DS_FH
Info: Selected device EP2C8Q208C7 for design "DS_FH"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 2 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 1269 of 1269 atoms in partition Top
    Info: Previous placement does not exist for 186 of 186 atoms in partition sld_hub:sld_hub_inst
Info: Detected 1 design partitions (excluding Top) used without floorplan location assignments.
    Info: Design partition sld_hub:sld_hub_inst has no floorplan location assignments
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5Q208C7 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 13 pins of 34 total pins
    Info: Pin DAC_clk not assigned to an exact location on the device
    Info: Pin QPSKout[9] not assigned to an exact location on the device
    Info: Pin QPSKout[8] not assigned to an exact location on the device
    Info: Pin QPSKout[7] not assigned to an exact location on the device
    Info: Pin QPSKout[6] not assigned to an exact location on the device
    Info: Pin QPSKout[5] not assigned to an exact location on the device
    Info: Pin QPSKout[4] not assigned to an exact location on the device
    Info: Pin QPSKout[3] not assigned to an exact location on the device
    Info: Pin QPSKout[2] not assigned to an exact location on the device
    Info: Pin QPSKout[1] not assigned to an exact location on the device
    Info: Pin QPSKout[0] not assigned to an exact location on the device
    Info: Pin sys_clk not assigned to an exact location on the device
    Info: Pin sys_reset not assigned to an exact location on the device
Info: Automatically promoted node sys_clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node DAC_clk
Info: Automatically promoted node sys_reset (placed in PIN 24 (CLK1, LVDSCLK0n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node clk_div:inst11|clkx4 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node clk_div:inst11|reset_DDS 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node ddscontrol:inst17|fq_ud
        Info: Destination node ddscontrol:inst17|w_clk
Info: Automatically promoted node clk_div:inst11|clk 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node MSC51:inst9|wr_enable1 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node MSC51:inst9|wr_enable1
Info: Automatically promoted node MSC51:inst9|wr_enable3 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node MSC51:inst9|wr_enable3
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:01
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 0 input, 11 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 8 total pin(s) used --  28 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 10 total pin(s) used --  25 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  34 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 11 total pin(s) used --  25 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to register delay of 4.233 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y8; Fanout = 2; REG Node = 'differential_encoder:inst5|dataq_3'
    Info: 2: + IC(1.984 ns) + CELL(0.322 ns) = 2.306 ns; Loc. = LAB_X21_Y3; Fanout = 10; COMB Node = 'inst13'
    Info: 3: + IC(1.187 ns) + CELL(0.740 ns) = 4.233 ns; Loc. = LAB_X24_Y7; Fanout = 1; REG Node = 'QPSK:inst1|tiaozhi:inst14|tempq[9]'
    Info: Total cell delay = 1.062 ns ( 25.09 % )
    Info: Total interconnect delay = 3.171 ns ( 74.91 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%
    Info: The peak interconnect region extends from location X23_Y0 to location X34_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:04
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 21 output pins without output pin load capacitance assignment
    Info: Pin "D0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "D1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "D2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "D3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "D4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "D5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "D6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "D7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "W_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FQ_UD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DAC_clk" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "QPSKout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 171 megabytes of memory during processing
    Info: Processing ended: Sun Jan 13 08:52:31 2008
    Info: Elapsed time: 00:00:40