ds_fh.hier_info

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

datak1[3] => cnt:inst18.datak1[3]
datak1[4] => cnt:inst18.datak1[4]
datak1[5] => cnt:inst18.datak1[5]
datak1[6] => cnt:inst18.datak1[6]
datak1[7] => cnt:inst18.datak1[7]
datak2[0] => cnt2:inst17.datak2[0]
datak2[1] => cnt2:inst17.datak2[1]
datak2[2] => cnt2:inst17.datak2[2]
datak2[3] => cnt2:inst17.datak2[3]
datak2[4] => cnt2:inst17.datak2[4]
datak2[5] => cnt2:inst17.datak2[5]
datak2[6] => cnt2:inst17.datak2[6]
datak2[7] => cnt2:inst17.datak2[7]


|DS_FH|QPSK:inst1|add:inst13
Iq[0] => Add0.IN10
Iq[1] => Add0.IN9
Iq[2] => Add0.IN8
Iq[3] => Add0.IN7
Iq[4] => Add0.IN6
Iq[5] => Add0.IN5
Iq[6] => Add0.IN4
Iq[7] => Add0.IN3
Iq[8] => Add0.IN2
Iq[9] => Add0.IN1
Qq[0] => Add0.IN20
Qq[1] => Add0.IN19
Qq[2] => Add0.IN18
Qq[3] => Add0.IN17
Qq[4] => Add0.IN16
Qq[5] => Add0.IN15
Qq[6] => Add0.IN14
Qq[7] => Add0.IN13
Qq[8] => Add0.IN12
Qq[9] => Add0.IN11
QPSKout[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
QPSKout[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|DS_FH|QPSK:inst1|tiaozhi:inst14
clk => tempq[0].CLK
clk => tempq[1].CLK
clk => tempq[2].CLK
clk => tempq[3].CLK
clk => tempq[4].CLK
clk => tempq[5].CLK
clk => tempq[6].CLK
clk => tempq[7].CLK
clk => tempq[8].CLK
clk => tempq[9].CLK
clk => tempi[0].CLK
clk => tempi[1].CLK
clk => tempi[2].CLK
clk => tempi[3].CLK
clk => tempi[4].CLK
clk => tempi[5].CLK
clk => tempi[6].CLK
clk => tempi[7].CLK
clk => tempi[8].CLK
clk => tempi[9].CLK
datai_1 => tempi~0.OUTPUTSELECT
datai_1 => tempi~1.OUTPUTSELECT
datai_1 => tempi~2.OUTPUTSELECT
datai_1 => tempi~3.OUTPUTSELECT
datai_1 => tempi~4.OUTPUTSELECT
datai_1 => tempi~5.OUTPUTSELECT
datai_1 => tempi~6.OUTPUTSELECT
datai_1 => tempi~7.OUTPUTSELECT
datai_1 => tempi~8.OUTPUTSELECT
datai_1 => tempi~9.OUTPUTSELECT
dataq_1 => tempq~0.OUTPUTSELECT
dataq_1 => tempq~1.OUTPUTSELECT
dataq_1 => tempq~2.OUTPUTSELECT
dataq_1 => tempq~3.OUTPUTSELECT
dataq_1 => tempq~4.OUTPUTSELECT
dataq_1 => tempq~5.OUTPUTSELECT
dataq_1 => tempq~6.OUTPUTSELECT
dataq_1 => tempq~7.OUTPUTSELECT
dataq_1 => tempq~8.OUTPUTSELECT
dataq_1 => tempq~9.OUTPUTSELECT
q1[0] => tempi~9.DATAA
q1[0] => Add0.IN8
q1[1] => tempi~8.DATAA
q1[1] => Add0.IN7
q1[2] => tempi~7.DATAA
q1[2] => Add0.IN6
q1[3] => tempi~6.DATAA
q1[3] => Add0.IN5
q1[4] => tempi~5.DATAA
q1[4] => Add0.IN4
q1[5] => tempi~4.DATAA
q1[5] => Add0.IN3
q1[6] => tempi~3.DATAA
q1[6] => Add0.IN2
q1[7] => tempi~2.DATAA
q1[7] => Add0.IN1
q1[8] => tempi~1.DATAA
q1[8] => Add0.IN0
q1[9] => tempi~0.DATAA
q1[9] => Add0.IN10
q2[0] => tempq~9.DATAA
q2[0] => Add1.IN8
q2[1] => tempq~8.DATAA
q2[1] => Add1.IN7
q2[2] => tempq~7.DATAA
q2[2] => Add1.IN6
q2[3] => tempq~6.DATAA
q2[3] => Add1.IN5
q2[4] => tempq~5.DATAA
q2[4] => Add1.IN4
q2[5] => tempq~4.DATAA
q2[5] => Add1.IN3
q2[6] => tempq~3.DATAA
q2[6] => Add1.IN2
q2[7] => tempq~2.DATAA
q2[7] => Add1.IN1
q2[8] => tempq~1.DATAA
q2[8] => Add1.IN0
q2[9] => tempq~0.DATAA
q2[9] => Add1.IN10
Iq[0] <= tempi[0].DB_MAX_OUTPUT_PORT_TYPE
Iq[1] <= tempi[1].DB_MAX_OUTPUT_PORT_TYPE
Iq[2] <= tempi[2].DB_MAX_OUTPUT_PORT_TYPE
Iq[3] <= tempi[3].DB_MAX_OUTPUT_PORT_TYPE
Iq[4] <= tempi[4].DB_MAX_OUTPUT_PORT_TYPE
Iq[5] <= tempi[5].DB_MAX_OUTPUT_PORT_TYPE
Iq[6] <= tempi[6].DB_MAX_OUTPUT_PORT_TYPE
Iq[7] <= tempi[7].DB_MAX_OUTPUT_PORT_TYPE
Iq[8] <= tempi[8].DB_MAX_OUTPUT_PORT_TYPE
Iq[9] <= tempi[9].DB_MAX_OUTPUT_PORT_TYPE
Qq[0] <= tempq[0].DB_MAX_OUTPUT_PORT_TYPE
Qq[1] <= tempq[1].DB_MAX_OUTPUT_PORT_TYPE
Qq[2] <= tempq[2].DB_MAX_OUTPUT_PORT_TYPE
Qq[3] <= tempq[3].DB_MAX_OUTPUT_PORT_TYPE
Qq[4] <= tempq[4].DB_MAX_OUTPUT_PORT_TYPE
Qq[5] <= tempq[5].DB_MAX_OUTPUT_PORT_TYPE
Qq[6] <= tempq[6].DB_MAX_OUTPUT_PORT_TYPE
Qq[7] <= tempq[7].DB_MAX_OUTPUT_PORT_TYPE
Qq[8] <= tempq[8].DB_MAX_OUTPUT_PORT_TYPE
Qq[9] <= tempq[9].DB_MAX_OUTPUT_PORT_TYPE


|DS_FH|QPSK:inst1|sin_rom:inst
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]


|DS_FH|QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_sc91:auto_generated.address_a[0]
address_a[1] => altsyncram_sc91:auto_generated.address_a[1]
address_a[2] => altsyncram_sc91:auto_generated.address_a[2]
address_a[3] => altsyncram_sc91:auto_generated.address_a[3]
address_a[4] => altsyncram_sc91:auto_generated.address_a[4]
address_a[5] => altsyncram_sc91:auto_generated.address_a[5]
address_a[6] => altsyncram_sc91:auto_generated.address_a[6]
address_a[7] => altsyncram_sc91:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_sc91:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_sc91:auto_generated.q_a[0]
q_a[1] <= altsyncram_sc91:auto_generated.q_a[1]
q_a[2] <= altsyncram_sc91:auto_generated.q_a[2]
q_a[3] <= altsyncram_sc91:auto_generated.q_a[3]
q_a[4] <= altsyncram_sc91:auto_generated.q_a[4]
q_a[5] <= altsyncram_sc91:auto_generated.q_a[5]
q_a[6] <= altsyncram_sc91:auto_generated.q_a[6]
q_a[7] <= altsyncram_sc91:auto_generated.q_a[7]
q_a[8] <= altsyncram_sc91:auto_generated.q_a[8]
q_a[9] <= altsyncram_sc91:auto_generated.q_a[9]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|DS_FH|QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated
address_a[0] => altsyncram_mk82:altsyncram1.address_a[0]
address_a[1] => altsyncram_mk82:altsyncram1.address_a[1]
address_a[2] => altsyncram_mk82:altsyncram1.address_a[2]
address_a[3] => altsyncram_mk82:altsyncram1.address_a[3]
address_a[4] => altsyncram_mk82:altsyncram1.address_a[4]
address_a[5] => altsyncram_mk82:altsyncram1.address_a[5]
address_a[6] => altsyncram_mk82:altsyncram1.address_a[6]
address_a[7] => altsyncram_mk82:altsyncram1.address_a[7]
clock0 => altsyncram_mk82:altsyncram1.clock0
q_a[0] <= altsyncram_mk82:altsyncram1.q_a[0]
q_a[1] <= altsyncram_mk82:altsyncram1.q_a[1]
q_a[2] <= altsyncram_mk82:altsyncram1.q_a[2]
q_a[3] <= altsyncram_mk82:altsyncram1.q_a[3]
q_a[4] <= altsyncram_mk82:altsyncram1.q_a[4]
q_a[5] <= altsyncram_mk82:altsyncram1.q_a[5]
q_a[6] <= altsyncram_mk82:altsyncram1.q_a[6]
q_a[7] <= altsyncram_mk82:altsyncram1.q_a[7]
q_a[8] <= altsyncram_mk82:altsyncram1.q_a[8]
q_a[9] <= altsyncram_mk82:altsyncram1.q_a[9]


|DS_FH|QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|altsyncram_mk82:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[5] => ram_block3a8.PORTAADDR5
address_a[5] => ram_block3a9.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[6] => ram_block3a8.PORTAADDR6
address_a[6] => ram_block3a9.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[7] => ram_block3a8.PORTAADDR7
address_a[7] => ram_block3a9.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[0] => ram_block3a8.PORTBADDR
address_b[0] => ram_block3a9.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[1] => ram_block3a8.PORTBADDR1
address_b[1] => ram_block3a9.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[2] => ram_block3a8.PORTBADDR2
address_b[2] => ram_block3a9.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[3] => ram_block3a8.PORTBADDR3
address_b[3] => ram_block3a9.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[4] => ram_block3a8.PORTBADDR4
address_b[4] => ram_block3a9.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[5] => ram_block3a8.PORTBADDR5
address_b[5] => ram_block3a9.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6