ds_fh.map.qmsg

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable m6_1.vhd(23) " "Warning (10492): VHDL Process Statement warning at m6_1.vhd(23): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "m6_1.vhd" "" { Text "E:/Quartus/DS_FH/m6_1.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m6_2.vhd 2 1 " "Warning: Using design file m6_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m6_2-generator_archi " "Info: Found design unit 1: m6_2-generator_archi" {  } { { "m6_2.vhd" "" { Text "E:/Quartus/DS_FH/m6_2.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 m6_2 " "Info: Found entity 1: m6_2" {  } { { "m6_2.vhd" "" { Text "E:/Quartus/DS_FH/m6_2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m6_2 DS_code:inst14\|Gold6:inst10\|m6_2:inst1 " "Info: Elaborating entity \"m6_2\" for hierarchy \"DS_code:inst14\|Gold6:inst10\|m6_2:inst1\"" {  } { { "Gold6.bdf" "inst1" { Schematic "E:/Quartus/DS_FH/Gold6.bdf" { { 152 208 304 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable m6_2.vhd(23) " "Warning (10492): VHDL Process Statement warning at m6_2.vhd(23): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "m6_2.vhd" "" { Text "E:/Quartus/DS_FH/m6_2.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Gold7.bdf 1 1 " "Warning: Using design file Gold7.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Gold7 " "Info: Found entity 1: Gold7" {  } { { "Gold7.bdf" "" { Schematic "E:/Quartus/DS_FH/Gold7.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Gold7 DS_code:inst14\|Gold7:inst11 " "Info: Elaborating entity \"Gold7\" for hierarchy \"DS_code:inst14\|Gold7:inst11\"" {  } { { "DS_code.bdf" "inst11" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 264 568 704 360 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m7_1.vhd 2 1 " "Warning: Using design file m7_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m7_1-generator_archi " "Info: Found design unit 1: m7_1-generator_archi" {  } { { "m7_1.vhd" "" { Text "E:/Quartus/DS_FH/m7_1.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 m7_1 " "Info: Found entity 1: m7_1" {  } { { "m7_1.vhd" "" { Text "E:/Quartus/DS_FH/m7_1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m7_1 DS_code:inst14\|Gold7:inst11\|m7_1:inst " "Info: Elaborating entity \"m7_1\" for hierarchy \"DS_code:inst14\|Gold7:inst11\|m7_1:inst\"" {  } { { "Gold7.bdf" "inst" { Schematic "E:/Quartus/DS_FH/Gold7.bdf" { { 56 184 280 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable m7_1.vhd(23) " "Warning (10492): VHDL Process Statement warning at m7_1.vhd(23): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "m7_1.vhd" "" { Text "E:/Quartus/DS_FH/m7_1.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m7_2.vhd 2 1 " "Warning: Using design file m7_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m7_2-generator_archi " "Info: Found design unit 1: m7_2-generator_archi" {  } { { "m7_2.vhd" "" { Text "E:/Quartus/DS_FH/m7_2.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 m7_2 " "Info: Found entity 1: m7_2" {  } { { "m7_2.vhd" "" { Text "E:/Quartus/DS_FH/m7_2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m7_2 DS_code:inst14\|Gold7:inst11\|m7_2:inst1 " "Info: Elaborating entity \"m7_2\" for hierarchy \"DS_code:inst14\|Gold7:inst11\|m7_2:inst1\"" {  } { { "Gold7.bdf" "inst1" { Schematic "E:/Quartus/DS_FH/Gold7.bdf" { { 168 184 280 264 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable m7_2.vhd(23) " "Warning (10492): VHDL Process Statement warning at m7_2.vhd(23): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "m7_2.vhd" "" { Text "E:/Quartus/DS_FH/m7_2.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Gold8.bdf 1 1 " "Warning: Using design file Gold8.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Gold8 " "Info: Found entity 1: Gold8" {  } { { "Gold8.bdf" "" { Schematic "E:/Quartus/DS_FH/Gold8.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Gold8 DS_code:inst14\|Gold8:inst12 " "Info: Elaborating entity \"Gold8\" for hierarchy \"DS_code:inst14\|Gold8:inst12\"" {  } { { "DS_code.bdf" "inst12" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 368 568 704 464 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m8_1.vhd 2 1 " "Warning: Using design file m8_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m8_1-generator_archi " "Info: Found design unit 1: m8_1-generator_archi" {  } { { "m8_1.vhd" "" { Text "E:/Quartus/DS_FH/m8_1.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 m8_1 " "Info: Found entity 1: m8_1" {  } { { "m8_1.vhd" "" { Text "E:/Quartus/DS_FH/m8_1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m8_1 DS_code:inst14\|Gold8:inst12\|m8_1:inst " "Info: Elaborating entity \"m8_1\" for hierarchy \"DS_code:inst14\|Gold8:inst12\|m8_1:inst\"" {  } { { "Gold8.bdf" "inst" { Schematic "E:/Quartus/DS_FH/Gold8.bdf" { { 56 280 376 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable m8_1.vhd(24) " "Warning (10492): VHDL Process Statement warning at m8_1.vhd(24): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "m8_1.vhd" "" { Text "E:/Quartus/DS_FH/m8_1.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m8_2.vhd 2 1 " "Warning: Using design file m8_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m8_2-generator_archi " "Info: Found design unit 1: m8_2-generator_archi" {  } { { "m8_2.vhd" "" { Text "E:/Quartus/DS_FH/m8_2.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 m8_2 " "Info: Found entity 1: m8_2" {  } { { "m8_2.vhd" "" { Text "E:/Quartus/DS_FH/m8_2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m8_2 DS_code:inst14\|Gold8:inst12\|m8_2:inst1 " "Info: Elaborating entity \"m8_2\" for hierarchy \"DS_code:inst14\|Gold8:inst12\|m8_2:inst1\"" {  } { { "Gold8.bdf" "inst1" { Schematic "E:/Quartus/DS_FH/Gold8.bdf" { { 160 280 376 256 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable m8_2.vhd(23) " "Warning (10492): VHDL Process Statement warning at m8_2.vhd(23): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "m8_2.vhd" "" { Text "E:/Quartus/DS_FH/m8_2.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Gold9.bdf 1 1 " "Warning: Using design file Gold9.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Gold9 " "Info: Found entity 1: Gold9" {  } { { "Gold9.bdf" "" { Schematic "E:/Quartus/DS_FH/Gold9.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Gold9 DS_code:inst14\|Gold9:inst13 " "Info: Elaborating entity \"Gold9\" for hierarchy \"DS_code:inst14\|Gold9:inst13\"" {  } { { "DS_code.bdf" "inst13" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 472 568 704 568 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m9_1.vhd 2 1 " "Warning: Using design file m9_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m9_1-gener