ds_fh.map.qmsg

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

{ "Warning" "WSGN_SEARCH_FILE" "M6.vhd 2 1 " "Warning: Using design file M6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 M6-generator_archi " "Info: Found design unit 1: M6-generator_archi" {  } { { "M6.vhd" "" { Text "E:/Quartus/DS_FH/M6.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 M6 " "Info: Found entity 1: M6" {  } { { "M6.vhd" "" { Text "E:/Quartus/DS_FH/M6.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "M6 DS_code:inst14\|M6:inst6 " "Info: Elaborating entity \"M6\" for hierarchy \"DS_code:inst14\|M6:inst6\"" {  } { { "DS_code.bdf" "inst6" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 160 392 512 256 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable M6.vhd(26) " "Warning (10492): VHDL Process Statement warning at M6.vhd(26): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "M6.vhd" "" { Text "E:/Quartus/DS_FH/M6.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "M7.vhd 2 1 " "Warning: Using design file M7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 M7-generator_archi " "Info: Found design unit 1: M7-generator_archi" {  } { { "M7.vhd" "" { Text "E:/Quartus/DS_FH/M7.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 M7 " "Info: Found entity 1: M7" {  } { { "M7.vhd" "" { Text "E:/Quartus/DS_FH/M7.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "M7 DS_code:inst14\|M7:inst7 " "Info: Elaborating entity \"M7\" for hierarchy \"DS_code:inst14\|M7:inst7\"" {  } { { "DS_code.bdf" "inst7" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 264 392 512 360 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable M7.vhd(26) " "Warning (10492): VHDL Process Statement warning at M7.vhd(26): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "M7.vhd" "" { Text "E:/Quartus/DS_FH/M7.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "M8.vhd 2 1 " "Warning: Using design file M8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 M8-generator_archi " "Info: Found design unit 1: M8-generator_archi" {  } { { "M8.vhd" "" { Text "E:/Quartus/DS_FH/M8.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 M8 " "Info: Found entity 1: M8" {  } { { "M8.vhd" "" { Text "E:/Quartus/DS_FH/M8.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "M8 DS_code:inst14\|M8:inst8 " "Info: Elaborating entity \"M8\" for hierarchy \"DS_code:inst14\|M8:inst8\"" {  } { { "DS_code.bdf" "inst8" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 368 392 512 464 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable M8.vhd(24) " "Warning (10492): VHDL Process Statement warning at M8.vhd(24): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "M8.vhd" "" { Text "E:/Quartus/DS_FH/M8.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "M9.vhd 2 1 " "Warning: Using design file M9.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 M9-generator_archi " "Info: Found design unit 1: M9-generator_archi" {  } { { "M9.vhd" "" { Text "E:/Quartus/DS_FH/M9.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 M9 " "Info: Found entity 1: M9" {  } { { "M9.vhd" "" { Text "E:/Quartus/DS_FH/M9.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "M9 DS_code:inst14\|M9:inst9 " "Info: Elaborating entity \"M9\" for hierarchy \"DS_code:inst14\|M9:inst9\"" {  } { { "DS_code.bdf" "inst9" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 472 392 512 568 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable M9.vhd(24) " "Warning (10492): VHDL Process Statement warning at M9.vhd(24): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "M9.vhd" "" { Text "E:/Quartus/DS_FH/M9.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Gold_Code.bdf 1 1 " "Warning: Using design file Gold_Code.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Gold_Code " "Info: Found entity 1: Gold_Code" {  } { { "Gold_Code.bdf" "" { Schematic "E:/Quartus/DS_FH/Gold_Code.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Gold_Code DS_code:inst14\|Gold_Code:inst15 " "Info: Elaborating entity \"Gold_Code\" for hierarchy \"DS_code:inst14\|Gold_Code:inst15\"" {  } { { "DS_code.bdf" "inst15" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 56 568 704 152 "inst15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m1.vhd 2 1 " "Warning: Using design file m1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m1-generator_archi " "Info: Found design unit 1: m1-generator_archi" {  } { { "m1.vhd" "" { Text "E:/Quartus/DS_FH/m1.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 m1 " "Info: Found entity 1: m1" {  } { { "m1.vhd" "" { Text "E:/Quartus/DS_FH/m1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m1 DS_code:inst14\|Gold_Code:inst15\|m1:inst " "Info: Elaborating entity \"m1\" for hierarchy \"DS_code:inst14\|Gold_Code:inst15\|m1:inst\"" {  } { { "Gold_Code.bdf" "inst" { Schematic "E:/Quartus/DS_FH/Gold_Code.bdf" { { 48 208 304 144 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable m1.vhd(27) " "Warning (10492): VHDL Process Statement warning at m1.vhd(27): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "m1.vhd" "" { Text "E:/Quartus/DS_FH/m1.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m2.vhd 2 1 " "Warning: Using design file m2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m2-generator_archi " "Info: Found design unit 1: m2-generator_archi" {  } { { "m2.vhd" "" { Text "E:/Quartus/DS_FH/m2.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 m2 " "Info: Found entity 1: m2" {  } { { "m2.vhd" "" { Text "E:/Quartus/DS_FH/m2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m2 DS_code:inst14\|Gold_Code:inst15\|m2:inst1 " "Info: Elaborating entity \"m2\" for hierarchy \"DS_code:inst14\|Gold_Code:inst15\|m2:inst1\"" {  } { { "Gold_Code.bdf" "inst1" { Schematic "E:/Quartus/DS_FH/Gold_Code.bdf" { { 176 208 304 272 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable m2.vhd(27) " "Warning (10492): VHDL Process Statement warning at m2.vhd(27): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "m2.vhd" "" { Text "E:/Quartus/DS_FH/m2.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Gold6.bdf 1 1 " "Warning: Using design file Gold6.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Gold6 " "Info: Found entity 1: Gold6" {  } { { "Gold6.bdf" "" { Schematic "E:/Quartus/DS_FH/Gold6.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Gold6 DS_code:inst14\|Gold6:inst10 " "Info: Elaborating entity \"Gold6\" for hierarchy \"DS_code:inst14\|Gold6:inst10\"" {  } { { "DS_code.bdf" "inst10" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 160 568 704 256 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "m6_1.vhd 2 1 " "Warning: Using design file m6_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 m6_1-generator_archi " "Info: Found design unit 1: m6_1-generator_archi" {  } { { "m6_1.vhd" "" { Text "E:/Quartus/DS_FH/m6_1.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 m6_1 " "Info: Found entity 1: m6_1" {  } { { "m6_1.vhd" "" { Text "E:/Quartus/DS_FH/m6_1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m6_1 DS_code:inst14\|Gold6:inst10\|m6_1:inst " "Info: Elaborating entity \"m6_1\" for hierarchy \"DS_code:inst14\|Gold6:inst10\|m6_1:inst\"" {  } { { "Gold6.bdf" "inst" { Schematic "E:/Quartus/DS_FH/Gold6.bdf" { { 48 208 304 144 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}