ds_fh.map.qmsg

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DS_code DS_code:inst14 " "Info: Elaborating entity \"DS_code\" for hierarchy \"DS_code:inst14\"" {  } { { "DS_FH.bdf" "inst14" { Schematic "E:/Quartus/DS_FH/DS_FH.bdf" { { 240 776 968 368 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mux_code.vhd 2 1 " "Warning: Using design file mux_code.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_code-one " "Info: Found design unit 1: mux_code-one" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mux_code " "Info: Found entity 1: mux_code" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_code DS_code:inst14\|mux_code:inst16 " "Info: Elaborating entity \"mux_code\" for hierarchy \"DS_code:inst14\|mux_code:inst16\"" {  } { { "DS_code.bdf" "inst16" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 304 808 984 624 "inst16" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp mux_code.vhd(19) " "Warning (10492): VHDL Process Statement warning at mux_code.vhd(19): signal \"temp\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DS_code mux_code.vhd(16) " "Warning (10631): VHDL Process Statement warning at mux_code.vhd(16): inferring latch(es) for signal or variable \"DS_code\", which holds its previous value in one or more paths through the process" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "DS_code mux_code.vhd(16) " "Info (10041): Verilog HDL or VHDL info at mux_code.vhd(16): inferred latch for \"DS_code\"" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mpn5.vhd 2 1 " "Warning: Using design file mpn5.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mpn5-generator_archi " "Info: Found design unit 1: mpn5-generator_archi" {  } { { "mpn5.vhd" "" { Text "E:/Quartus/DS_FH/mpn5.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mpn5 " "Info: Found entity 1: mpn5" {  } { { "mpn5.vhd" "" { Text "E:/Quartus/DS_FH/mpn5.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpn5 DS_code:inst14\|mpn5:inst " "Info: Elaborating entity \"mpn5\" for hierarchy \"DS_code:inst14\|mpn5:inst\"" {  } { { "DS_code.bdf" "inst" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 56 208 320 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable mpn5.vhd(24) " "Warning (10492): VHDL Process Statement warning at mpn5.vhd(24): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "mpn5.vhd" "" { Text "E:/Quartus/DS_FH/mpn5.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mpn6.vhd 2 1 " "Warning: Using design file mpn6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mpn6-generator_archi " "Info: Found design unit 1: mpn6-generator_archi" {  } { { "mpn6.vhd" "" { Text "E:/Quartus/DS_FH/mpn6.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mpn6 " "Info: Found entity 1: mpn6" {  } { { "mpn6.vhd" "" { Text "E:/Quartus/DS_FH/mpn6.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpn6 DS_code:inst14\|mpn6:inst1 " "Info: Elaborating entity \"mpn6\" for hierarchy \"DS_code:inst14\|mpn6:inst1\"" {  } { { "DS_code.bdf" "inst1" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 160 208 320 256 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable mpn6.vhd(26) " "Warning (10492): VHDL Process Statement warning at mpn6.vhd(26): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "mpn6.vhd" "" { Text "E:/Quartus/DS_FH/mpn6.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mpn7.vhd 2 1 " "Warning: Using design file mpn7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mpn7-generator_archi " "Info: Found design unit 1: mpn7-generator_archi" {  } { { "mpn7.vhd" "" { Text "E:/Quartus/DS_FH/mpn7.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mpn7 " "Info: Found entity 1: mpn7" {  } { { "mpn7.vhd" "" { Text "E:/Quartus/DS_FH/mpn7.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpn7 DS_code:inst14\|mpn7:inst2 " "Info: Elaborating entity \"mpn7\" for hierarchy \"DS_code:inst14\|mpn7:inst2\"" {  } { { "DS_code.bdf" "inst2" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 264 208 320 360 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable mpn7.vhd(26) " "Warning (10492): VHDL Process Statement warning at mpn7.vhd(26): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "mpn7.vhd" "" { Text "E:/Quartus/DS_FH/mpn7.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mpn8.vhd 2 1 " "Warning: Using design file mpn8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mpn8-generator_archi " "Info: Found design unit 1: mpn8-generator_archi" {  } { { "mpn8.vhd" "" { Text "E:/Quartus/DS_FH/mpn8.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mpn8 " "Info: Found entity 1: mpn8" {  } { { "mpn8.vhd" "" { Text "E:/Quartus/DS_FH/mpn8.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpn8 DS_code:inst14\|mpn8:inst3 " "Info: Elaborating entity \"mpn8\" for hierarchy \"DS_code:inst14\|mpn8:inst3\"" {  } { { "DS_code.bdf" "inst3" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 368 208 320 464 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable mpn8.vhd(26) " "Warning (10492): VHDL Process Statement warning at mpn8.vhd(26): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "mpn8.vhd" "" { Text "E:/Quartus/DS_FH/mpn8.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mpn9.vhd 2 1 " "Warning: Using design file mpn9.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mpn9-generator_archi " "Info: Found design unit 1: mpn9-generator_archi" {  } { { "mpn9.vhd" "" { Text "E:/Quartus/DS_FH/mpn9.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mpn9 " "Info: Found entity 1: mpn9" {  } { { "mpn9.vhd" "" { Text "E:/Quartus/DS_FH/mpn9.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpn9 DS_code:inst14\|mpn9:inst4 " "Info: Elaborating entity \"mpn9\" for hierarchy \"DS_code:inst14\|mpn9:inst4\"" {  } { { "DS_code.bdf" "inst4" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 472 208 320 568 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable mpn9.vhd(26) " "Warning (10492): VHDL Process Statement warning at mpn9.vhd(26): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "mpn9.vhd" "" { Text "E:/Quartus/DS_FH/mpn9.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "M5.vhd 2 1 " "Warning: Using design file M5.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 M5-generator_archi " "Info: Found design unit 1: M5-generator_archi" {  } { { "M5.vhd" "" { Text "E:/Quartus/DS_FH/M5.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 M5 " "Info: Found entity 1: M5" {  } { { "M5.vhd" "" { Text "E:/Quartus/DS_FH/M5.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "M5 DS_code:inst14\|M5:inst5 " "Info: Elaborating entity \"M5\" for hierarchy \"DS_code:inst14\|M5:inst5\"" {  } { { "DS_code.bdf" "inst5" { Schematic "E:/Quartus/DS_FH/DS_code.bdf" { { 56 392 512 152 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "enable M5.vhd(25) " "Warning (10492): VHDL Process Statement warning at M5.vhd(25): signal \"enable\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "M5.vhd" "" { Text "E:/Quartus/DS_FH/M5.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}