cnt2.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt2 is 
port(clk:in std_logic;
	datak2:in std_logic_vector(7 downto 0);
	adder2:out std_logic_vector(7 downto 0));
end;
architecture one of cnt2 is
signal adder:std_logic_vector(7 downto 0):="11010000";
begin 

process(clk)
begin	
	if clk'event and clk='1' then
		adder<=adder+datak2;
	end if;
end process;
adder2<=adder;
end one;