ds_fh.tan.summary

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.523 ns
From           : WR
To             : MSC51:inst9|wr_enable2
From Clock     : --
To Clock       : P26
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.349 ns
From           : initialization:inst|temp2
To             : D6
From Clock     : sys_reset
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 5.044 ns
From           : sys_clk
To             : DAC_clk
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.821 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'P26'
Slack          : N/A
Required Time  : None
Actual Time    : 78.31 MHz ( period = 12.770 ns )
From           : MSC51:inst9|latch_out2[4]
To             : DS_code:inst14|mux_code:inst16|DS_code
From Clock     : P26
To Clock       : P26
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 137.17 MHz ( period = 7.290 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[1]
To             : sld_hub:sld_hub_inst|hub_tdo~reg0
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'sys_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 151.15 MHz ( period = 6.616 ns )
From           : differential_encoder:inst5|dataq_3
To             : QPSK:inst1|tiaozhi:inst14|tempq[0]
From Clock     : sys_clk
To Clock       : sys_clk
Failed Paths   : 0

Type           : Clock Setup: 'sys_reset'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 380.08 MHz ( period = 2.631 ns )
From           : ddscontrol:inst17|current_state[3]
To             : ddscontrol:inst17|w_clk
From Clock     : sys_reset
To Clock       : sys_reset
Failed Paths   : 0

Type           : Clock Hold: 'P26'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : MSC51:inst9|latch_out2[1]
To             : DS_code:inst14|mux_code:inst16|DS_code
From Clock     : P26
To Clock       : P26
Failed Paths   : 3

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 3

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