cnt.vhd

来自「扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is 
port(clk:in std_logic;
	datak1:in std_logic_vector(7 downto 0);
	adder1:out std_logic_vector(7 downto 0));
end;
architecture one of cnt is
signal adderr:std_logic_vector(7 downto 0):="00010000";
begin 

process(clk)
begin
if clk'event and clk='1' then
		adderr<=adderr+datak1;
	end if;
end process;
adder1<=adderr;
end one;