add.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
entity add is
port(Iq,Qq:in std_logic_vector(9 downto 0);
	QPSKout:out std_logic_vector(9 downto 0));
end;

architecture one of add is
signal temp:std_logic_vector(9 downto 0);

begin

process(Iq,Qq)
begin
	QPSKout<=Iq+Qq;
end process;

end;