ddscontrol.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity ddscontrol is
port(
	clk_DDS,reset_DDS:in std_logic;
	hopset:in std_logic_vector(4 downto 0);
	d0,d1,d2,d3,d4,d5,d6,d7:out std_logic;
	w_clk,fq_ud:out std_logic
	);
end ddscontrol;

architecture one of ddscontrol is
signal segment:std_logic_vector(31 downto 0);
signal current_state,next_state:integer range 0 to 11;
signal wclk,fqud:std_logic;
signal d0_t,d1_t,d2_t,d3_t,d4_t,d5_t,d6_t,d7_t:std_logic;
begin

process(reset_DDS,clk_DDS)
begin
	if(reset_DDS='1')then
		current_state<=0;
	elsif(clk_DDS'event and clk_DDS='1')then
		current_state<=next_state;
		w_clk<=wclk;
		fq_ud<=fqud;
	end if;
end process;

process(hopset)
variable a:integer range 0 to 19;
begin
	a:=conv_integer("000" & hopset(4 downto 0));
	case a is
		when 0=>segment<="00111001011010111011100110001100";
		when 1=>segment<="00111010100101011110100111100001";
		when 2=>segment<="00111011110000000001101000110110";
		when 3=>segment<="00111100111010100100101010001100";
		when 4=>segment<="00111110000101000111101011100001";
		when 5=>segment<="00111111001111101010101100110110";
		when 6=>segment<="01000000011010001101101110001011";
		when 7=>segment<="01000001100100110000101111100000";
		when 8=>segment<="01000010101111010011110000110110";
		when 9=>segment<="01000011111001110110110010001011";
		when 10=>segment<="01000101000100011001110011100000";
		when 11=>segment<="01000110001110111100110100110101";
		when 12=>segment<="01000111011001011111110110001010";
		when 13=>segment<="01001000100100000010110111100000";
		when 14=>segment<="01001001101110100101111000110101";
		when 15=>segment<="01001010111001001000111010001010";
		when 16=>segment<="01001100000011101011111011011111";
		when 17=>segment<="01001101001110001110111100110100";
		when 18=>segment<="01001110011000110001111110001010";
		when 19=>segment<="01001111100011010100111111011111";
		when others=>segment<=null;
	end case;
end process;

process(segment,current_state)
begin
	case current_state is
	when 0=>
		next_state<=1;
		d7_t<='0';d6_t<='0';d5_t<='0';d4_t<='0';
		d3_t<='0';d2_t<='0';d1_t<='0';d0_t<='0';
		wclk<='0';
		fqud<='0';
	when 1=>
		next_state<=2;
		d7_t<='0';d6_t<='0';d5_t<='0';d4_t<='0';
		d3_t<='0';d2_t<='0';d1_t<='0';d0_t<='0';
		wclk<='1';
		fqud<='1';
	when 2=>
		next_state<=3;
		d7_t<='0';d6_t<='0';d5_t<='0';d4_t<='0';
		d3_t<='0';d2_t<='0';d1_t<='0';d0_t<='0';
		wclk<='0';
		fqud<='1';
	when 3=>
		next_state<=4;
		d7_t<=segment(31);d6_t<=segment(30);d5_t<=segment(29);d4_t<=segment(28);
		d3_t<=segment(27);d2_t<=segment(26);d1_t<=segment(25);d0_t<=segment(24);
		wclk<='1';
		fqud<='1';
	when 4=>
		next_state<=5;
		d7_t<=segment(31);d6_t<=segment(30);d5_t<=segment(29);d4_t<=segment(28);
		d3_t<=segment(27);d2_t<=segment(26);d1_t<=segment(25);d0_t<=segment(24);
		wclk<='0';
		fqud<='1';
	when 5=>
		next_state<=6;
		d7_t<=segment(23);d6_t<=segment(22);d5_t<=segment(21);d4_t<=segment(20);
		d3_t<=segment(19);d2_t<=segment(18);d1_t<=segment(17);d0_t<=segment(16);
		wclk<='1';
		fqud<='0';
	when 6=>
		next_state<=7;
		d7_t<=segment(23);d6_t<=segment(22);d5_t<=segment(21);d4_t<=segment(20);
		d3_t<=segment(19);d2_t<=segment(18);d1_t<=segment(17);d0_t<=segment(16);
		wclk<='0';
		fqud<='0';
	when 7=>
		next_state<=8;
		d7_t<=segment(15);d6_t<=segment(14);d5_t<=segment(13);d4_t<=segment(12);
		d3_t<=segment(11);d2_t<=segment(10);d1_t<=segment(9);d0_t<=segment(8);
		wclk<='1';
		fqud<='0';
	when 8=>
		next_state<=9;
		d7_t<=segment(15);d6_t<=segment(14);d5_t<=segment(13);d4_t<=segment(12);
		d3_t<=segment(11);d2_t<=segment(10);d1_t<=segment(9);d0_t<=segment(8);
		wclk<='0';
		fqud<='0';
	when 9=>
		next_state<=10;
		d7_t<=segment(7);d6_t<=segment(6);d5_t<=segment(5);d4_t<=segment(4);
		d3_t<=segment(3);d2_t<=segment(2);d1_t<=segment(1);d0_t<=segment(0);
		wclk<='1';
		fqud<='0';
	when 10=>
		next_state<=11;
		d7_t<=segment(7);d6_t<=segment(6);d5_t<=segment(5);d4_t<=segment(4);
		d3_t<=segment(3);d2_t<=segment(2);d1_t<=segment(1);d0_t<=segment(0);
		wclk<='0';
		fqud<='0';
	when 11=>
		next_state<=11;
		d7_t<='0';d6_t<='0';d5_t<='0';d4_t<='0';
		d3_t<='0';d2_t<='0';d1_t<='0';d0_t<='0';
		wclk<='0';
		fqud<='0';	
	end case;
end process;

d7<=d7_t;
d6<=d6_t;
d5<=d5_t;
d4<=d4_t;
d3<=d3_t;
d2<=d2_t;
d1<=d1_t;
d0<=d0_t;

end one;