ds_fh.map.summary

来自「扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Sun Jan 13 08:51:26 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : DS_FH
Top-level Entity Name : DS_FH
Family : Cyclone II
Total logic elements : 616
    Total combinational functions : 616
    Dedicated logic registers : 595
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Embedded Multiplier 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge