mux_framer.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux_framer is
port(notready:in std_logic;
	datai_a,dataq_a,datai_b,dataq_b:in std_logic;
    datai_2,dataq_2:out std_logic);
end;
architecture one of mux_framer is
begin
process(notready)
begin
if notready='1' then
	datai_2<=datai_a;
	dataq_2<=dataq_a;
else
	datai_2<=datai_b; 
	dataq_2<=dataq_b;
end if;
end process;
--datai_2<=datai_a when notready='1' else datai_b;
--dataq_2<=dataq_a when notready='1' else dataq_b;
end;