piso8.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity piso8 is
port(
	clk,notready:in std_logic;
	dataout:in std_logic_vector(7 downto 0);
	data:out std_logic);
end;

architecture one of piso8 is
	signal cnt:std_logic_vector(2 downto 0);--8进制计数器，用于控制数据的输出
	signal q:std_logic_vector(7 downto 0);--8位寄存器
begin
process(clk)
begin
	if clk'event and clk='1' then
		cnt<=cnt+1;
	end if;
end process;

process(clk,notready)
begin
	if notready='1' then
		q<="00000000";
	elsif clk'event and clk='1' then
		if cnt>"000" then--如果计数器大于“000”则移位
			q(7 downto 1)<=q(6 downto 0);
		elsif cnt="000" then--如果计数器等于“000”则加载数据
			q<=dataout;
		end if;
	end if;
end process;
data<=q(7);
end;