msc51.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity MSC51 is
port(
     wr,p26,ale:in std_logic;
     p0:in std_logic_vector(7 downto 0);
     dataout:out std_logic_vector(7 downto 0);
     data_sel:out std_logic;
	 code_style:out std_logic_vector(1 downto 0);
	 code_len:out std_logic_vector(2 downto 0);
	 datak:out std_logic_vector(7 downto 0)
	);
end MSC51;

architecture one of MSC51 is
signal wr_enable1,wr_enable2,wr_enable3:std_logic;
signal latch_address,latch_out1,latch_out2,latch_out3:std_logic_vector(7 downto 0);
begin
	process(ale)--地址锁存进程
	begin
		if ale'event and ale='0' then--ale下降沿将p0口的地址锁入锁存器latch-address中
			latch_address<=p0;
		end if;
	end process;
	
	process(p26,latch_address)--wr写信号译码进程1
	begin
		if (p26='0') then
			if (latch_address="00000000")then
				wr_enable1<=wr;--写允许
			else 
				wr_enable1<='1';--写禁止
			end if;
		end if;
	end process;
	
	process(wr_enable1)--数据写入寄存器1
	begin
		if wr_enable1'event and wr_enable1='1' then
			latch_out1<=p0;
		else 
			latch_out1<=latch_out1;
		end if;
	end process;
	
	process(p26,latch_address)--wr写信号译码进程2
	begin
		if (p26='0') then
			if(latch_address="00000001")then
				wr_enable2<=wr;
			else
				wr_enable2<='1';

			end if;
		end if;
	end process;
	
	process(wr_enable2)--数据写入寄存器2
	begin
		if wr_enable2'event and wr_enable2='1' then
			latch_out2<=p0;
		else 
			latch_out2<=latch_out2;
		end if;
	end process;
		
	process(p26,latch_address)--wr写信号译码进程2
	begin
		if (p26='0') then
			if(latch_address="00000010")then
				wr_enable3<=wr;
			else
				wr_enable3<='1';

			end if;
		end if;
	end process;
	
	process(wr_enable3)--数据写入寄存器3
	begin
		if wr_enable3'event and wr_enable3='1' then
			latch_out3<=p0;
		else 
			latch_out3<=latch_out3;
		end if;
	end process;
	
dataout<=latch_out1;
data_sel<=latch_out2(0);
code_style<=latch_out2(2 downto 1);
code_len<=latch_out2(5 downto 3);
datak<=latch_out3;
	
end one;