ds_fh.tan.rpt

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                             ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                                    ; From                                               ; To                                                                      ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; 7.523 ns                                       ; WR                                                 ; MSC51:inst9|wr_enable2                                                  ; --                           ; P26                          ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 20.349 ns                                      ; initialization:inst|temp2                          ; D6                                                                      ; sys_reset                    ; --                           ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 5.044 ns                                       ; sys_clk                                            ; DAC_clk                                                                 ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 1.821 ns                                       ; altera_internal_jtag~TMSUTAP                       ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'P26'                          ; N/A                                      ; None          ; 78.31 MHz ( period = 12.770 ns )               ; MSC51:inst9|latch_out2[4]                          ; DS_code:inst14|mux_code:inst16|DS_code                                  ; P26                          ; P26                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 137.17 MHz ( period = 7.290 ns )               ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[1] ; sld_hub:sld_hub_inst|hub_tdo~reg0                                       ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'sys_clk'                      ; N/A                                      ; None          ; 151.15 MHz ( period = 6.616 ns )               ; differential_encoder:inst5|dataq_3                 ; QPSK:inst1|tiaozhi:inst14|tempq[0]                                      ; sys_clk                      ; sys_clk                      ; 0            ;
; Clock Setup: 'sys_reset'                    ; N/A                                      ; None          ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; ddscontrol:inst17|current_state[3]                 ; ddscontrol:inst17|w_clk                                                 ; sys_reset                    ; sys_reset                    ; 0            ;
; Clock Hold: 'P26'                           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; MSC51:inst9|latch_out2[1]                          ; DS_code:inst14|mux_code:inst16|DS_code                                  ; P26                          ; P26                          ; 3            ;
; Total number of failed paths                ;                                          ;               ;                                                ;                                                    ;                                                                         ;                              ;                              ; 3            ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8Q208C7        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+