m9_2.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

LIBRARY ieee;       
USE ieee.std_logic_1164.all;    
USE ieee.std_logic_arith.all;

ENTITY m9_2 IS    ---------x9+x6+x4+x3+1  [3 4 6 9]
PORT(clkx1024:IN STD_LOGIC;
	notready:IN STD_LOGIC;
	pn:OUT STD_LOGIC);
END m9_2;

ARCHITECTURE generator_archi OF m9_2 IS 
SIGNAL count:INTEGER RANGE 0 TO 512;
SIGNAL enable:STD_LOGIC;
BEGIN

PROCESS(notready,count,clkx1024)
VARIABLE shift:STD_LOGIC_VECTOR(8 downto 0);
VARIABLE tmp:STD_LOGIC;
BEGIN
IF(notready='1'OR count=512) THEN
  pn<='0';
  shift:="100000000";  
ELSIF(enable='1') THEN
   IF(clkx1024'event AND clkx1024='1')THEN
     tmp:=shift(0) XOR shift(3)XOR shift(5)XOR shift(6);
     pn<=tmp;     
     FOR i IN 0 TO 7 LOOP
       shift(i):=shift(i+1);
     END LOOP;
     shift(8):=tmp;
   END IF;
 END IF;
END PROCESS;

PROCESS(notready,clkx1024)
BEGIN
   IF notready='1' THEN
     count<=0;
   ELSIF(clkx1024'event AND clkx1024='1') THEN
    	IF count=512 THEN
			count<=1;
   		ELSE count<=count+1;
  		END IF;
	END IF;
END PROCESS;

PROCESS(count,clkx1024,notready)
BEGIN
	IF notready='1' THEN
 		 enable<='1';
	elsif(clkx1024'event AND clkx1024='0') THEN
		IF(count=511) THEN
		enable<='0';
		ELSIF(count=512) THEN
		enable<='1';
  		END IF;
	END IF;
END PROCESS;
END generator_archi;