mux_code.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
entity mux_code is
port(m5,m6,m7,m8,m9:in std_logic;
	M_5,M_6,M_7,M_8,M_9:in std_logic;
	gold5,gold6,gold7,gold8,gold9:in std_logic;
	code_style:in std_logic_vector(1 downto 0);
	code_len:in std_logic_vector(2 downto 0);
    DS_code:out std_logic);
end;

architecture one of mux_code is
signal temp:std_logic_vector(4 downto 0);
begin

process(code_style,code_len,m5,m6,m7,m8,m9,M_5,M_6,M_7,M_8,M_9,gold5,gold6,gold7,gold8,gold9)
begin
    temp<=code_len&code_style;
    case temp is
		when "00101"=>DS_code<=m5;
		when "00110"=>DS_code<=M_5;
		when "00111"=>DS_code<=gold5;
		when "01001"=>DS_code<=m6;
		when "01010"=>DS_code<=M_6;
		when "01011"=>DS_code<=gold6;
		when "01101"=>DS_code<=m7;
		when "01110"=>DS_code<=M_7;
		when "01111"=>DS_code<=gold7;		
		when "10001"=>DS_code<=m8;
		when "10010"=>DS_code<=M_8;
		when "10011"=>DS_code<=gold8;
		when "10101"=>DS_code<=m9;
		when "10110"=>DS_code<=M_9;
		when "10111"=>DS_code<=gold9;				
		when others=>null;
	end case;

end process;
end;