shaping_filter.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
PACKAGE coeffs IS
TYPE coeff_arr IS ARRAY(0 to 24)OF SIGNED (12 DOWNTO 0);
CONSTANT coeff:coeff_arr:=("1111110111010",
"1111110110000",
"1111111000001",
"1111111101111",
"0000000110101",
"0000010000011",
"0000011000100",
"0000011100000",
"0000011000110",
"0000001101010",
"1111111010010",
"1111100010001",
"1111001001011",
"1110110110010",
"1110101110110",
"1110111000111",
"1111011000010",
"0000001101111",
"0001010111001",
"0010101110010",
"0100001010011",
"0101100001011",
"0110101000101",
"0111010111100",
"0111100111111");
FUNCTION CACULATION(SIGNAL LL,RR:STD_LOGIC) RETURN SIGNED;
END coeffs;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
PACKAGE BODY coeffs IS
FUNCTION CACULATION(SIGNAL LL,RR:STD_LOGIC) RETURN SIGNED IS
	VARIABLE temp:std_logic_vector(1 downto 0);
	VARIABLE result:SIGNED(2 DOWNTO 0);
BEGIN
	temp:=LL&RR;
		CASE temp IS
			WHEN "00"=>
				result:="010";
			WHEN "11"=>
				result:="110";
			WHEN "01"=>
				result:="000";
			WHEN "10"=>
				result:="000";
			WHEN "ZZ"=>
				result:="000";
			WHEN "1Z"=>
				result:="111";
	    	WHEN "0Z"=>
				result:="001";
			WHEN "Z1"=>
				result:="111";
			WHEN "Z0"=>
				result:="001";
			WHEN OTHERS=>
				result:="000";
			END CASE;
		RETURN result;
	end;
end coeffs;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

USE work.coeffs.all;

ENTITY shaping_filter is
	PORT(
		clkx8192:in std_logic;
		datai_4:in std_logic;
		dataq_4:in std_logic;
		start:in std_logic;
		datai_5:out std_logic_vector(15 downto 0);
		dataq_5:out std_logic_vector(15 downto 0)
	);
end shaping_filter;

ARCHITECTURE filter_archi of shaping_filter is
	signal shifti,shiftq:std_logic_vector(47 downto 0);
	signal count:integer range 0 to 8;
	signal tempi,tempq:std_logic;
begin

process(start,clkx8192)
begin
	if start='1' then
		count<=0;
	elsif clkx8192'event and clkx8192='1' then
		if count=8 then
			count<=1;
		else count<=count+1;
		end if;
	end if;
end process;

process(count,datai_4,dataq_4)
begin
	if count=1 then
		tempi<=datai_4;tempq<=dataq_4;
	else tempi<='L';tempq<='L';
	end if;
end process;

process(start,clkx8192)
begin
	if start='1' then
	 shifti<=(OTHERS=>'L');shiftq<=(OTHERS=>'L');
	ELSIF clkx8192'event and clkx8192='1' then
		for i in 0 to 46 loop
		 shifti(i+1)<=shifti(i);
		 shiftq(i+1)<=shiftq(i);
		end loop;
		 shifti(0)<=tempi;shiftq(0)<=tempq;
	end if;
end process;

process(start,clkx8192,shifti)
	variable acci:signed(15 downto 0);
	variable xi:signed(15 downto 0);
begin
	if start='1' then
	 datai_5<=(OTHERS=>'0');
	 acci:=(OTHERS=>'0');
	 xi:=(OTHERS=>'0');
	ELSIF clkx8192'event and clkx8192='1' then
	 acci:=(CACULATION(tempi,shifti(47)))*coeff(0);
		for i in 0 to 22 loop
		 xi:=(CACULATION(shifti(i),shifti(46-i)))*coeff(i+1);
		 acci:=acci+xi;
		end loop;
		if(shifti(23)='0') then
		 acci:=acci+CONV_SIGNED(coeff(24),16);
		elsif shifti(23)='1' then
		 acci:=acci-CONV_SIGNED(coeff(18),16);
		end if;
	datai_5<=conv_std_logic_vector(acci,16);
	end if;
end process;

process(start,clkx8192,shiftq)
	variable accq:signed(15 downto 0);
	variable xq:signed(15 downto 0);
begin
	if start='1' then
		dataq_5<=(OTHERS=>'0');
		accq:=(OTHERS=>'0');
		xq:=(OTHERS=>'0');
	elsif clkx8192'event and clkx8192='1' then
		accq:=(CACULATION(tempq,shiftq(47)))*coeff(0);
		for i in 0 to 22 loop
			xq:=(CACULATION(shiftq(i),shiftq(46-i)))*coeff(i+1);
			accq:=accq+xq;
		end loop;
		if shiftq(23)='0' then
			accq:=accq+CONV_SIGNED(coeff(24),16);
		elsif shiftq(23)='1' then
			accq:=accq-CONV_SIGNED(coeff(18),16);
		end if;
		dataq_5<=conv_std_logic_vector(accq,16);
	end if;
end process;

end filter_archi;