m2.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

LIBRARY ieee;       
USE ieee.std_logic_1164.all;    
USE ieee.std_logic_arith.all;

ENTITY m2 IS   -------------x5+x3+x2+x+1  [1 2 3 5] 
PORT(clkx1024:IN STD_LOGIC;
	 notready:IN STD_LOGIC;
	 pn:OUT STD_LOGIC
	);
END m2;

ARCHITECTURE generator_archi OF m2 IS 
	SIGNAL count:INTEGER RANGE 0 TO 32;
	SIGNAL enable:STD_LOGIC;
	SIGNAL clk:STD_LOGIC;
BEGIN

clk<=clkx1024; 

PROCESS(notready,count,clk)
	VARIABLE shift:STD_LOGIC_VECTOR(4 downto 0);
	VARIABLE tmp:STD_LOGIC;
BEGIN
	IF(notready='1'OR count=32) THEN
	  pn<='0';
	  shift:="10000";  
	ELSIF(enable='1') THEN
		 IF(clk'event AND clk='1')THEN
		     tmp:=shift(0) XOR shift(2)XOR shift(3)XOR shift(4);
		     pn<=tmp;     
		     FOR i IN 0 TO 3 LOOP
		       shift(i):=shift(i+1);
		     END LOOP;
		     shift(4):=tmp;
		 END IF;
	 END IF;
END PROCESS;

PROCESS(notready,clkx1024)
BEGIN
   IF notready='1' THEN
     count<=0;
   ELSIF(clkx1024'event AND clkx1024='1') THEN
    	IF count=32 THEN
			count<=1;
   		ELSE count<=count+1;
  		END IF;
	END IF;
END PROCESS;

PROCESS(count,clkx1024,notready)
BEGIN
	IF notready='1' THEN
 		 enable<='1';
	elsif(clkx1024'event AND clkx1024='0') THEN
		IF(count=31) THEN
		enable<='0';
		ELSIF(count=32) THEN
		enable<='1';
	    END IF;
	END IF;
END PROCESS;
END generator_archi;