m7_2.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

LIBRARY ieee;       
USE ieee.std_logic_1164.all;    
USE ieee.std_logic_arith.all;

ENTITY m7_2 IS    ----------x7+x4+x3+x2+1 [2 3 4 7]
PORT(clkx1024:IN STD_LOGIC;
	 notready:IN STD_LOGIC;
	 pn:OUT STD_LOGIC);
END m7_2;

ARCHITECTURE generator_archi OF m7_2 IS 
	SIGNAL cnt:INTEGER RANGE 0 TO 128;
	SIGNAL enable:STD_LOGIC;
BEGIN

PROCESS(notready,cnt,clkx1024)
	VARIABLE shift:STD_LOGIC_VECTOR(6 downto 0);
	VARIABLE tmp:STD_LOGIC;
BEGIN
	IF(notready='1'OR cnt=128) THEN
	  pn<='0';
	  shift:="1000000";  
	ELSIF(enable='1') THEN
		 IF(clkx1024'event AND clkx1024='1')THEN
		     tmp:=shift(0) XOR shift(3) XOR shift(4)XOR shift(5);
		     pn<=tmp;     
		     FOR i IN 0 TO 5 LOOP
		       shift(i):=shift(i+1);
		     END LOOP;
		     shift(6):=tmp;
		 END IF;
	 END IF;
END PROCESS;

PROCESS(notready,clkx1024)
BEGIN
   IF notready='1' THEN
     cnt<=0;
   ELSIF(clkx1024'event AND clkx1024='1') THEN
    	IF cnt=128 THEN
			cnt<=1;
   		ELSE cnt<=cnt+1;
  		END IF;
	END IF;
END PROCESS;

PROCESS(cnt,clkx1024,notready)
BEGIN
	IF notready='1' THEN
 		 enable<='1';
	elsif(clkx1024'event AND clkx1024='0') THEN
		IF(cnt=127) THEN
		enable<='0';
		ELSIF(cnt=128) THEN
		enable<='1';
	    END IF;
	END IF;
END PROCESS;
END generator_archi;