differential_encoder.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity differential_encoder is
port(
	clkx4:in std_logic;
	datai_2,dataq_2:in std_logic;
	notready:in std_logic;
	datai_3,dataq_3:buffer std_logic
	);
end differential_encoder;

architecture encode_archi of differential_encoder is
	signal tempi,tempq:std_logic;
begin

process(notready,datai_2,datai_3,dataq_2,dataq_3)
begin
	if(notready='1')then
		tempi<='0';tempq<='0';
	else
		tempi<=datai_2 xor datai_3;
		tempq<=dataq_2 xor dataq_3;
	end if;
end process;

process(clkx4,tempi,tempq,notready)
begin
	if(notready='1')then
		datai_3<='0';dataq_3<='0';
	elsif(clkx4'event and clkx4='1')then
		datai_3<=tempi;dataq_3<=tempq;
	end if;
end process;

end encode_archi;