📄 atlpll_waveforms.html
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<title>Sample Waveforms for atlPLL.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file atlPLL.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design atlPLL.vhd. The design atlPLL.vhd has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>
<CENTER><img src=atlPLL_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3>When input port ARESET is asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted. </P>
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