board.c

最高实时取样率2M点/秒

 
 // -------------------------------------------------------------------------
 //	Timer/Counter 1
 //
 
 // TCCRnA - Timer/Counter1(3) Control Register A
 // COMnA[1:0]: 	Compare Output Mode for Channel A
 // COMnB[1:0]: 	Compare Output Mode for Channel B
 // COMnC[1:0]: 	Compare Output Mode for Channel C
 //	Non-PWM Mode:
 //		00 - Normal port operation, OCnA/OCnB/OCnC disconnected.
 //		01 - Toggle OCnA/OCnB/OCnC on Compare Match.
 //		10 - Clear OCnA/OCnB/OCnC on Compare Match (Set output to low level).
 //		11 - Set OCnA/OCnB/OCnC on Compare Match (Set output to high level).
 //
 //	Fast PWM Mode:
 //		00 - Normal port operation, OCnA/OCnB/OCnC disconnected.
 //		01 - WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB/OCnC disconnected 
 //			(normal port operation). For all other WGMn settings, normal port operation,
//			OCnA/OCnB/OCnC disconnected.
 //		10 - Clear OCnA/OCnB/OCnC on Compare Match, set OCnA/OCnB/OCnC at TOP.
 //		11 - Set OCnA/OCnB/OCnC on Compare Match, clear OCnA/OCnB/OCnC at TOP.
 //
 //	Phase Correct and Phase and Frequency Correct PWM Mode:
 //		00 - Normal port operation, OCnA/OCnB/OCnC disconnected.
 //		01 - WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match, OCnB/OCnC 
 //			disconnected (normal port operation). Forr all other WGMn settings, normal 
 //			port operation, OCnA/OCnB/OCnC disconnected.
 //		10 - Clear OCnA/OCnB/OCnC on Compare Match when upcounting. 
 //			Set OCnA/OCnB/OCnC on Compare Match when downcounting.
 //		11 - Set OCnA/OCnB/OCnC on Compare Match when up-counting.
 //			Clear OCnA/OCnB/OCnC on Compare Match when downcounting.
 //
 // WGMn[1:0]: 	Waveform Generation Mode. Combined with WGMn[3:2]  in the TCCRnB
 //				Mode			TOP			Update of OCRnX		TOVn Set
 //                      --------------------------------------------------------------
 //		0000 - 	Normal 			0xFFFF 		Immediate 			MAX
 //		0001 - 	PWM, PC8 		0x00FF 		TOP 					BOTTOM
 //		0010 - 	PWM, PC9 		0x01FF 		TOP 					BOTTOM
 //		0011 - 	PWM, PC10		0x03FF 		TOP 					BOTTOM
 //		0100 - 	CTC 			OCRnA 		Immediate 			MAX
 //		0101 - 	Fast PWM, 8-bit 	0x00FF 		TOP 					TOP
 //		0110 - 	Fast PWM, 9-bit 	0x01FF 		TOP 					TOP
 //		0111 - 	Fast PWM, 10-bit 	0x03FF 		TOP 					TOP
 //		1000 - 	PWM, P&F C		ICRn 		BOTTOM 				BOTTOM
 //		1001 - 	PWM, P&F C		OCRnA 		BOTTOM 				BOTTOM
 //		1010 - 	PWM, PC			ICRn		TOP 					BOTTOM
 //		1011 - 	PWM, PC			OCRnA 		TOP 					BOTTOM
 //		1100 - 	CTC 			ICRn 		Immediate 			MAX
 //		1101 - 	(Reserved) 		– 			– 					–
 //		1110 - 	Fast PWM 		ICRn 		TOP 					TOP
 //		1111 - 	Fast PWM 		OCRnA 		TOP 					TOP
 //
 // Current Settings:
 //	CTC mode using ICR1 (WGM3[3:0] = 1100)
 TCCR1A = (0<<COM1A1)|(0<<COM1A0) |(0<<COM1B1) |(0<<COM1B0) 
 		|(0<<COM1C1) |(0<<COM1C0) |(0<<WGM11) |(0<<WGM10);
 
 // TCCRnB - Timer/Counter1(3) Control Register B
 //	ICNCn: 		Input Capture Noise Canceler
 //	ICESn: 		Input Capture Edge Select. 0 = falling, 1 = rising.
 //	WGMn[3:2]: 	Waveform Generation Mode
 //	CSn2:0: 		Clock Select
 //		000 - No clock source (Timer/counter stopped).
 //		001 - clkI/O/1 (No prescaling)
 //		010 - clkI/O/8 (From prescaler)
 //		011 - clkI/O/64 (From prescaler)
 //		100 - clkI/O/256 (From prescaler)
 //		101 - clkI/O/1024 (From prescaler)
 //		110 - External clock source on Tn pin. Clock on falling edge.
 //		111 - External clock source on Tn pin. Clock on rising edge.
 //
 // Current Settings:
 // -- No prescaling (CS1[2:0] = 001)
 TCCR1B = (0<<ICNC1)|(0<<ICES1)|(1<<WGM13)|(1<<WGM12)
 		|(0<<CS12)|(0<<CS11)|(1<<CS10);

 // TCCRnC - Timer/Counter1(3) Control Register C
 //	FOCnA: 	Force Output Compare for Channel A
 //	FOCnB: 	Force Output Compare for Channel B
 //	FOCnC: 	Force Output Compare for Channel C
 //
 TCCR1C = (0<<FOC1A)|(0<<FOC1B)|(0<<FOC1C);

 // TCNT1H and TCNT1L - Timer/Counter1
 //
 TCNT1H = 0x00;
 TCNT1L = 0x00;

 // OCR1AH and OCR1AL - Output Compare Register 1A
 // 
 OCR1AH = 0x00;
 OCR1AL = 0x00;

 // OCR1BH and OCR1BL - Output Compare Register 1 B
 // 
 OCR1BH = 0x00;
 OCR1BL = 0x00;

 // OCR1CH and OCR1CL - Output Compare Register 1 C
 // 
 OCR1CH = 0x00;
 OCR1CL = 0x00;

 // ICR1H and ICR1L - Input Capture Register 1
 //
 ICR1H = 0x00;
 ICR1L = 0x00;

 // ----------------------------------------------------------------------
 //	Timer/Counter 2
 //
 // TCCR2 - Timer/Counter Control Register
 //	FOC2: 		Force Output Compare
 //	WGM2[1:0]: 	Waveform Generation Mode
 //			Mode		TOP			Update of OCR2	TOV2 Set
 //		00 - Normal		0xFF 		Immediate 		MAX
 //		01 - PWM, PC		0xFF 		TOP 				BOTTOM
 //		10 - CTC 		OCR2 		Immediate 		MAX
 //		11 - Fast PWM 	0xFF 		TOP 				MAX
 //
 //	COM2[1:0]: 	Compare Match Output Mode
 //		Non-PWM Mode:
 //			00 - Normal port operation, OC2 disconnected.
 //			01 - Toggle OC2 on Compare Match.
 //			10 - Clear OC2 on Compare Match.
 //			11 - Set OC2 on Compare Match.
 //
 //		Fast PWM Mode:
 //			00 - Normal port operation, OC2 disconnected.
 //			01 - Reserved
 //			10 - Clear OC2 on Compare Match, set OC2 at TOP.
 //			11 - Set OC2 on Compare Match, clear OC2 at TOP.
 //
 //		Phase Correct PWM Mode:
 //			00 - Normal port operation, OC2 disconnected.
 //			01 - Reserved
 //			10 - Clear OC2 on Compare Match when up-counting. Set OC2 on Compare
 //				Match when downcounting.
 //			11 - Set OC2 on Compare Match when up-counting. Clear OC2 on Compare
 //				Match when downcounting.
 //	CS22:0: 		Clock Select
 //			000 - No clock source (Timer/counter stopped).
 //			001 - clkI/O/(No prescaling)
 //			010 - clkI/O/8 (From prescaler)
 //			011 - clkI/O/64 (From prescaler)
 //			100 - clkI/O/256 (From prescaler)
 //			101 - clkI/O/1024 (From prescaler)
 //			110 - External clock source on T2 pin. Clock on falling edge.
 //			111 - External clock source on T2 pin. Clock on rising edge.
 //
 // Current settings:
 //	CTC mode (WGM2[1:0] = 10)
 //	Toggle OC@ on compare match (COM2[1:0] = 01)
 //	NO prescaling (CS2[2:0] = 001)
 //	Toggle OC2 every 5us - 100KHz square wave to generate neg voltage for LCD
 //		(OCR2 = 100)
 TCCR2 = (0<<FOC2)|(0<<WGM20)|(0<<COM21)|(0<<COM20)
 		|(1<<WGM21)|(0<<CS22)|(0<<CS21)|(1<<CS20);

 // TCNT2 - Timer/Counter Register
 //	
 TCNT2 = 0x00;

 // OCR2 - Output Compare Register
 //
 OCR2 = 200;

 
 // ----------------------------------------------------------------------
 //	Timer/Counter 3 (See descriptions in Timer/Counter 1 for meanings of settings)
 //
  // TCCRnA - Timer/Counter1(3) Control Register A
 // COMnA[1:0]: 	Compare Output Mode for Channel A
 // COMnB[1:0]: 	Compare Output Mode for Channel B
 // COMnC[1:0]: 	Compare Output Mode for Channel C
 //	Non-PWM Mode:
 //		00 - Normal port operation, OCnA/OCnB/OCnC disconnected.
 //		01 - Toggle OCnA/OCnB/OCnC on Compare Match.
 //		10 - Clear OCnA/OCnB/OCnC on Compare Match (Set output to low level).
 //		11 - Set OCnA/OCnB/OCnC on Compare Match (Set output to high level).
 //
 //	Fast PWM Mode:
 //		00 - Normal port operation, OCnA/OCnB/OCnC disconnected.
 //		01 - WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB/OCnC disconnected 
 //			(normal port operation). For all other WGMn settings, normal port operation,
//			OCnA/OCnB/OCnC disconnected.
 //		10 - Clear OCnA/OCnB/OCnC on Compare Match, set OCnA/OCnB/OCnC at TOP.
 //		11 - Set OCnA/OCnB/OCnC on Compare Match, clear OCnA/OCnB/OCnC at TOP.
 //
 //	Phase Correct and Phase and Frequency Correct PWM Mode:
 //		00 - Normal port operation, OCnA/OCnB/OCnC disconnected.
 //		01 - WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match, OCnB/OCnC 
 //			disconnected (normal port operation). Forr all other WGMn settings, normal 
 //			port operation, OCnA/OCnB/OCnC disconnected.
 //		10 - Clear OCnA/OCnB/OCnC on Compare Match when upcounting. 
 //			Set OCnA/OCnB/OCnC on Compare Match when downcounting.
 //		11 - Set OCnA/OCnB/OCnC on Compare Match when up-counting.
 //			Clear OCnA/OCnB/OCnC on Compare Match when downcounting.
 //
 // WGMn[1:0]: 	Waveform Generation Mode. Combined with WGMn[3:2]  in the TCCRnB
 //				Mode			TOP			Update of OCRnX		TOVn Set
 //                      --------------------------------------------------------------
 //		0000 - 	Normal 			0xFFFF 		Immediate 			MAX
 //		0001 - 	PWM, PC8 		0x00FF 		TOP 					BOTTOM
 //		0010 - 	PWM, PC9 		0x01FF 		TOP 					BOTTOM
 //		0011 - 	PWM, PC10		0x03FF 		TOP 					BOTTOM
 //		0100 - 	CTC 			OCRnA 		Immediate 			MAX
 //		0101 - 	Fast PWM, 8-bit 	0x00FF 		TOP 					TOP
 //		0110 - 	Fast PWM, 9-bit 	0x01FF 		TOP 					TOP
 //		0111 - 	Fast PWM, 10-bit 	0x03FF 		TOP 					TOP
 //		1000 - 	PWM, P&F C		ICRn 		BOTTOM 				BOTTOM
 //		1001 - 	PWM, P&F C		OCRnA 		BOTTOM 				BOTTOM
 //		1010 - 	PWM, PC			ICRn		TOP 					BOTTOM
 //		1011 - 	PWM, PC			OCRnA 		TOP 					BOTTOM
 //		1100 - 	CTC 			ICRn 		Immediate 			MAX
 //		1101 - 	(Reserved) 		– 			– 					–
 //		1110 - 	Fast PWM 		ICRn 		TOP 					TOP
 //		1111 - 	Fast PWM 		OCRnA 		TOP 					TOP
 //
 // Current setting:
 // 	Fast PWM, 8-bit [WGM1[3:0] = 0101] 
 //	OC3C for TrigLevel (COM3C[1:0] = 10)
 //	OC3B for VPos (COM3B[1:0] = 10) 
 //	OC3A for AVCC- generation (COM3A[1:0] = 10)
 TCCR3A = (1<<COM3A1)|(0<<COM3A0) |(1<<COM3B1) |(0<<COM3B0) 
 		|(1<<COM3C1) |(0<<COM3C0) |(0<<WGM31) |(1<<WGM30);
 
 // TCCRnB - Timer/Counter1(3) Control Register B
 //	ICNCn: 		Input Capture Noise Canceler
 //	ICESn: 		Input Capture Edge Select
 //	WGMn[3:2]: 	Waveform Generation Mode
 //	CSn2:0: 		Clock Select
 //		000 - No clock source (Timer/counter stopped).
 //		001 - clkI/O/1 (No prescaling)
 //		010 - clkI/O/8 (From prescaler)
 //		011 - clkI/O/64 (From prescaler)
 //		100 - clkI/O/256 (From prescaler)
 //		101 - clkI/O/1024 (From prescaler)
 //		110 - External clock source on Tn pin. Clock on falling edge.
 //		111 - External clock source on Tn pin. Clock on rising edge.
 //
 // Current Settings:
 //	No prescaling (CS3[2:0] = 001)
 TCCR3B = (0<<ICNC3)|(0<<ICES3)|(0<<WGM33)|(1<<WGM32)
 		|(0<<CS32)|(0<<CS31)|(1<<CS30);

 // TCCRnC - Timer/Counter1(3) Control Register C
 //	FOCnA: 	Force Output Compare for Channel A
 //	FOCnB: 	Force Output Compare for Channel B
 //	FOCnC: 	Force Output Compare for Channel C
 //
 TCCR3C = (0<<FOC3A)|(0<<FOC3B)|(0<<FOC3C);

 // TCNT3H and TCNT3L - Timer/Counter3
 //
 TCNT3H = 0x00;
 TCNT3L = 0x00;
 // OCR3AH and OCR3AL - Output Compare Register 3 A
 // 
 OCR3AH = 0x00;
 OCR3AL = 0x60;	// for 50% duty-cycle

 // OCR3BH and OCR3BL - Output Compare Register 3 B
 // 
 OCR3BH = 0x00;
 OCR3BL = 0x00;

 // OCR3CH and OCR3CL - Output Compare Register 3 C
 // 
 OCR3CH = 0x00;
 OCR3CL = 0x00;

 // ICR3H and ICR3L - Input Capture Register 3
 //
 ICR3H = 0x00;
 ICR3L = 0x00;

 // -------------------------------------------------------------------
 //	Interrupt settings for Timer 1/2/3
 //
 // TIMSK - Timer/Counter Interrupt Mask Register
 //	OCIE2: 	1 = Timer/Counter2 Output Compare Match Interrupt Enable [TIMSK.7]
 //	TOIE2: 	1 = Timer/Counter2 Overflow Interrupt Enable [TIMSK.6]
 //	TICIE1: 	1 = Timer/Counter1, Input Capture Interrupt Enable [TIMSK.5]
 //	OCIE1A: 	1 = Timer/Counter1, Output Compare A Match Interrupt Enable [TIMSK.4]
 //	OCIE1B: 	1 = Timer/Counter1, Output Compare B Match Interrupt Enable [TIMSK.3]
 //	TOIE1: 	1 = Timer/Counter1, Overflow Interrupt Enable [TIMSK.2]
 // 	OCIE0: 	1 = Timer/Counter0 Output Compare Match Interrupt Enable [TIMSK.1]
 //	TOIE0: 	1 = Timer/Counter0 Overflow Interrupt Enable [TIMSK.0]
 TIMSK = (0<<OCIE2)|(0<<TOIE2)|(0<<TICIE1)|(0<< OCIE1A)
 	      	|(0<<OCIE1B)|(0<< TOIE1)|(0<< OCIE0)|(0<< TOIE0);

 // ETIMSK - Extended Timer/Counter Interrupt Mask Register
 //	TICIE3: 	Timer/Counter3, Input Capture Interrupt Enable
 //	OCIE3A: 	Timer/Counter3, Output Compare A Match Interrupt Enable
 //	OCIE3B: 	Timer/Counter3, Output Compare B Match Interrupt Enable
 //	TOIE3: 	Timer/Counter3, Overflow Interrupt Enable
 //	OCIE3C: 	Timer/Counter3, Output Compare C Match Interrupt Enable
 //	OCIE1C: 	Timer/Counter1, Output Compare C Match Interrupt Enable
 //
 ETIMSK = (0<<TICIE3)|(0<<OCIE3A)|(0<<OCIE3B)|(0<<TOIE3)
 		|(0<<OCIE3C)|(0<<OCIE1C);

 // TIFR - Timer/Counter Interrupt Flag Register
 //	OCF2: 	Output Compare Flag 2
 //	TOV2: 	Timer/Counter2 Overflow Flag
 //	ICF1: 	Timer/Counter1, Input Capture Flag
 //	OCF1A: 	Timer/Counter1, Output Compare A Match Flag
 //	OCF1B: 	Timer/Counter1, Output Compare B Match Flag
 //	TOV1: 	Timer/Counter1, Overflow Flag
 //	OCF0: 	Output Compare Flag 0
 //	TOV0: 	Timer/Counter0 Overflow Flag
 TIFR = (1<<OCF2)|(1<<TOV2)|(1<<ICF1)|(1<<OCF1A)
 		|(1<<OCF1B)|(1<<TOV1)|(1<<OCF0)|(1<<TOV0);

 // ETIFR - Extended Timer/Counter Interrupt Flag Register
 //	ICF3: 	Timer/Counter3, Input Capture Flag
 //	OCF3A: 	Timer/Counter3, Output Compare A Match Flag
 //	OCF3B: 	Timer/Counter3, Output Compare B Match Flag
 //	TOV3: 	Timer/Counter3, Overflow Flag
 //	OCF3C: 	Timer/Counter3, Output Compare C Match Flag
 //	OCF1C: 	Timer/Counter1, Output Compare C Match Flag
 //	
 ETIFR = (1<<ICF3)|(1<<OCF3A)|(1<<OCF3B)|(1<<TOV3)|(1<<OCF3C)|(1<<OCF1C);

}

// ------------------------------------------------------------------------
//	Delay specified time in ms 
//	Based on PCA0 Module 4	
// ------------------------------------------------------------------------
void DelayTimer(U16 ms)
{
 	
}