📄 board.c
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// UDRE1: 1 = USART Data Register Empty [UCSR1A.5]
// FE1: 1 = Frame Error [UCSR1A.4]
// DOR1: 1 = Data Over Run [UCSR1A.3]
// UPE1: 1 = USART Parity Error [UCSR1A.2]
// U2X1: 1 = Double USART transmission speed (for asynchronous only) [UCSR1A.1]
// MPCM1: 1 = Multiprocessor Communication Mode [UCSR1A.0]
//
// UCSR1A defaults are all bits zero.
UCSR1A = (0<<TXC1)|(0<<U2X1)|(0<<MPCM1);
// UCSR1B - USART Control and Status Register B
// RXCIE1: 1 = Receive complete interrupt enable [UCSR1B.7]
// TXCIE1: 1 = Transmit complete interrupt enable [UCSR1B.6]
// UDRIE1: 1 = USART Data Register Empty interrupt enable [UCSR1B.5]
// RXEN1: 1 = Receiver enable [UCSR1B.4]
// TXEN1: 1 = Transmitter enable [UCSR1B.3]
// UCSZ12: Character size, combined with UCSZ1.[1:0] in UCSR1C [UCSR1B.2]
// RXB81: 1 = Receive Date Bit 8 [UCSR1B.1]
// TXB81: 1 = Transmit Date Bit 8 [UCSR1B.0]
//
// UCSR1B defaults are all bits zero.
// -- Enable receiver
// -- Enable transmitter
UCSR1B = (0<<RXCIE1)|(0<<TXCIE1)|(0<<UDRIE1)|(1<<RXEN1)
|(1<<TXEN1)|(0<<UCSZ12)|(0<<TXB81);
// UCSR1C - USART Control and Status Register C
// UMSEL1: 1 = Asynchronous, 0 = Synchronous [UCSR1C.6]
// UPM1.[1:0]: Parity Mode [UCSR1C.[5:4]]
// 00 = Disabled
// 01 = Reserved
// 10 = Enabled, even parity
// 11 = Enabled, odd parity
// USBS1: Stop bit select, 0 = 1 stop bit, 1 = 2 stop bits [UCSR1C.3]
// UCSZ1.[1:0]: Character size, combined with UCSZ12 in UCSR1B [UCSR1C.2]
// 000 = 5-bit
// 001 = 6-bit
// 010 = 7-bit
// 011 = 8-bit
// 100 = Reserved
// 101 = Reserved
// 110 = Reserved
// 111 = 9-bit
// UCPOL1: Clock pority, for synchronous mode only [UCSR1C.0] (See datasheet)
//
UCSR1C = (0<<UMSEL1)|(0<<UPM11)|(0<<UPM10)|(0<<USBS1)
|(1<<UCSZ11)|(1<<UCSZ10)|(0<<UCPOL1);
// Setup baudrate
UBRR1H = (((F_CPU / 16) / Uart1_Baud) - 1) >> 8;
UBRR1L = (((F_CPU / 16) / Uart1_Baud) - 1) & 0x00FF;
}
//-----------------------------------------------------------------------------// Output one byte to Uart 0 - polling method
//-----------------------------------------------------------------------------//void u0putc(U8 ch)
{
while(!BitTest8(UCSR0A, (1<<UDRE0))) {
}
UDR0 = ch;
}
//-----------------------------------------------------------------------------// Output one byte to Uart 1 - polling method
//-----------------------------------------------------------------------------//void u1putc(U8 ch)
{
while(!BitTest8(UCSR1A, (1<<UDRE1))) {
}
UDR1 = ch;
}
//-----------------------------------------------------------------------------// Receive one byte from Uart 0 - polling method
//-----------------------------------------------------------------------------//U8 u0getc(void)
{
while(!BitTest8(UCSR0A, (1<<RXC0))) {
}
return (UDR0);
}
//-----------------------------------------------------------------------------// Receive one byte from Uart 1 - polling method
//-----------------------------------------------------------------------------//U8 u1getc(void)
{
while(!BitTest8(UCSR1A, (1<<RXC1))) {
}
return (UDR1);
}
//-----------------------------------------------------------------------------// Output zero terminated string to Uart 0 or Uart 1 - polling method
//-----------------------------------------------------------------------------//void uputs(U8 *s, U8 UartNum)
{
if(UartNum == 0) {
while(*s != 0) {
u0putc(*s);
s++;
}
}
else {
while(*s != 0) {
u1putc(*s);
s++;
}
}
}
//-----------------------------------------------------------------------------
// Receive state check
// Return 1 if received data ready, otherwise return 0.
//-----------------------------------------------------------------------------
//
U8 u0rcheck(void)
{
if(BitTest8(UCSR0A, (1<<RXC0))) {
return 1;
}
return 0;
}
U8 u1rcheck(void)
{
if(BitTest8(UCSR1A, (1<<RXC1))) {
return 1;
}
return 0;
}
U8 u1rcheck_and_get(void)
{
if(BitTest8(UCSR1A, (1<<RXC1))) {
return (UDR1);
}
return 0;
}
//-----------------------------------------------------------------------------
// Comp_Init//-----------------------------------------------------------------------------//void Comp_Init(void){
// Special Function IO Register - SFIOR
// ACME: 1 = Analog Comparator Multiplexer Enable
// When this bit is written logic one and the ADC is switched off
// (ADEN in ADCSRA is zero), the ADC multiplexer selects the
// negative input to the Analog Comparator. When this bit is written
// logic zero, AIN1 is applied to the negative input of the Analog Comparator.
//
// Current settings:
// -- ACME = 0 to use AIN1 as comparator input
// (Actual setting is done in Misc_Init())
// ACSR - Analog Comparator Control and Status Register
// ACD: 1 = Analog Comparator Disable (ACSR.7)
// ACBG: 1 = fixed bandgap reference voltage applies positive input. Otherwise (ACSR.6)
// AIN0 is connected to positive input.
// ACO: Analog Comparator Output with 1-2 clock delay. (ACSR.5)
// ACI: Analog Comparator Interrupt Flag. Set by hardware based on ACS[1:0] (ACSR.4)
// ACIE: 1 = Analog Comparator Interrupt Enable (ACSR.3)
// ACIC: 1 = Analog Comparator Input Capture Enable (ACSR.2)
// ACIS[1:0]: Analog Comparator Interrupt Mode Select (ACSR.[1:0])
// 00 - Comparator Interrupt on Output Toggle.
// 01 - Reserved
// 10 - Comparator Interrupt on Falling Output Edge.
// 11 - Comparator Interrupt on Rising Output Edge.
//
// Current Settings:
//
ACSR = (0 << ACD)|(0 << ACBG)|(0 << ACO)|(0 << ACI)|(0 << ACIE)
|(0 <<ACIC)|(0 << ACIS1)|(0 << ACIS0);
}
//-----------------------------------------------------------------------------// ADC0_Init//-----------------------------------------------------------------------------//void ADC_Init (void)
{ //ADMUX - ADC Multiplexer Selection Register
// Bit 7:6 – REFS1:0: Reference Selection Bits
// 0 0 - AREF, Internal Vref turned off.
// 0 1 - AVCC with external capacitor at AREF pin.
// 1 0 - Reserved
// 1 1 - Internal 2.56V Voltage Reference with external capacitor at AREF pin.
// Bit 5 – ADLAR: ADC Left Adjust Result. 1 = Left adjust
// Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
// MUX4..0 Single Ended Pos Diff. Input Neg Diff. Input Gain
// 00000 ADC0
// 00001 ADC1
// 00010 ADC2
// 00011 ADC3
// 00100 ADC4
// 00101 ADC5
// 00110 ADC6
// 00111 ADC7
// 01000 ADC0 ADC0 10x
// 01001 ADC1 ADC0 10x
// 01010 ADC0 ADC0 200x
// 01011 ADC1 ADC0 200x
// 01100 ADC2 ADC2 10x
// 01101 ADC3 ADC2 10x
// 01110 ADC2 ADC2 200x
// 01111 ADC3 ADC2 200x
// 10000 ADC0 ADC1 1x
// 10001 ADC1 ADC1 1x
// 10010 ADC2 ADC1 1x
// 10011 ADC3 ADC1 1x
// 10100 ADC4 ADC1 1x
// 10101 ADC5 ADC1 1x
// 10110 ADC6 ADC1 1x
// 10111 ADC7 ADC1 1x
// 11000 ADC0 ADC2 1x
// 11001 ADC1 ADC2 1x
// 11010 ADC2 ADC2 1x
// 11011 ADC3 ADC2 1x
// 11100 ADC4 ADC2 1x
// 11101 ADC5 ADC2 1x
// 11110 1.22V (VBG)
// 11111 0V (GND)
//
//
ADMUX = (0<<REFS1)|(0<<REFS0)|(0<<ADLAR)
|(0<<MUX4)|(0<<MUX3)|(1<<MUX2)|(0<<MUX1)|(0<<MUX0);
//ADCSRA - ADC Control and Status Register A
// Bit 7 – ADEN: ADC Enable. 1 = enable.
// Bit 6 – ADSC: ADC Start Conversion. 1 = start conversion
// Bit 5 – ADATE: ADC Auto Trigger Enable. 1 = auto trigger enabled
// Bit 4 – ADIF: ADC Interrupt Flag
// Bit 3 – ADIE: ADC Interrupt Enable. 1 = enabled
// Bits [2:0] – ADPS2:0: ADC Prescaler Select Bits
// ADPS[2:0] Division Factor
// 0 0 0 2
// 0 0 1 2
// 0 1 0 4
// 0 1 1 8
// 1 0 0 16
// 1 0 1 32
// 1 1 0 64
// 1 1 1 128
ADCSRA = (0<<ADEN)|(0<<ADSC)|(0<<ADATE)|(0<<ADIF)
|(0<<ADIE)|(0<<ADPS2)|(0<<ADPS1)|(0<<ADPS0);
//DCSRB - ADC Control and Status Register B
// Bits 7:3 – Res: Reserved Bits
// Bit 2:0 – ADTS[2:0]: ADC Auto Trigger Source
// ADTS[2:0] Trigger Source
// 0 0 0 Free Running mode
// 0 0 1 Analog Comparator
// 0 1 0 External Interrupt Request 0
// 0 1 1 Timer/Counter0 Compare Match
// 1 0 0 Timer/Counter0 Overflow
// 1 0 1 Timer/Counter1 Compare Match B
// 1 1 0 Timer/Counter1 Overflow
// 1 1 1 Timer/Counter1 Capture Event
ADCSRB = (0<<ADTS2)|(0<<ADTS1)|(0<<ADTS0);
}
//-----------------------------------------------------------------------------
// Timer_Init
//-----------------------------------------------------------------------------//void Timer_Init (void)
{
// -------------------------------------------------------------------------
// Timer/Counter 0
//
// TCCR0 - Timer/Counter Control Register
// FOC0: Force Output Compare
// WGM0[1:0]: Waveform Generation Mode
// Mode TOP Update of OCR0 TOV0 Set
// 00 - Normal 0xFF Immediate MAX
// 01 - PWM, PC 0xFF TOP BOTTOM
// 10 - CTC OCR0 Immediate MAX
// 11 - Fast PWM 0xFF TOP MAX
//
// COM0[1:0]: Compare Match Output Mode
// Non-PWM Mode:
// 00 - Normal port operation, OC0 disconnected.
// 01 - Toggle OC0 on Compare Match.
// 10 - Clear OC0 on Compare Match.
// 11 - Set OC0 on Compare Match.
//
// Fast PWM Mode:
// 00 - Normal port operation, OC0 disconnected.
// 01 - Reserved
// 10 - Clear OC0 on Compare Match, set OC0 at TOP.
// 11 - Set OC0 on Compare Match, clear OC0 at TOP.
//
// Phase Correct PWM Mode:
// 00 - Normal port operation, OC0 disconnected.
// 01 - Reserved
// 10 - Clear OC0 on Compare Match when up-counting. Set OC0 on Compare
// Match when downcounting.
// 11 - Set OC0 on Compare Match when up-counting. Clear OC0 on Compare
// Match when downcounting.
// CS02:0: Clock Select
// 000 - No clock source (Timer/counter stopped).
// 001 - clkI/O/(No prescaling)
// 010 - clkI/O/8 (From prescaler)
// 011 - clkI/O/32 (From prescaler)
// 100 - clkI/O/64 (From prescaler)
// 101 - clkI/O/128 (From prescaler)
// 110 - clkI/O/256 (From prescaler)
// 111 - clkI/O/1024 (From prescaler)
//
// Current settings:
// Mode = CTC (WGM0[1:0] = 10)
// 1/128 prescaling (CS0[2:0] = 101)
// Enable TV0 interrupt (TIMSK.0 = 1)
// Toggle OC0 (PB4) at compare match
TCCR0 = (0<<FOC0)|(0<<WGM00)|(0<<COM01)|(1<<COM00)
|(1<<WGM01)|(1<<CS02)|(0<<CS01)|(1<<CS00);
// TCNT0 - Timer/Counter Register
//
TCNT0 = 0x00;
// OCR0 - Output Compare Register
//
// Set OCR0 to 160 to produce ~1ms interval at 20MHz clock
// (128 * 156)/20 = 998.4us
OCR0 = 156-1;
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