board.c

最高实时取样率2M点/秒

//////////////////////////////////////////////////////////////////////////////
//
// 	Filename:	Board.c
//	Version:		0.01
//	Data:		2005.12.20
//
//	Author:		Liu, Zemin
//	Company:	zmLAB
//
//-----------------------------------------------------------------------------
//
// 	Target: 		ATmega64
// 	Tool chain: 	WinAvr (GCC-AVR)
//
//
//-----------------------------------------------------------------------------
//	Required files:
//
//-----------------------------------------------------------------------------
//	Notes:
//
//
//-----------------------------------------------------------------------------
//	Revision History:
//		V0.01		2005.12.20
//		1. First created.
//
///////////////////////////////////////////////////////////////////////////////
//
//-----------------------------------------------------------------------------
// 	Includes
//-----------------------------------------------------------------------------

#include <inttypes.h>
#include "avr/io.h"
#include	"avr/Pgmspace.h"
#include "Common.h"
#include "Board.h"
#include <avr/interrupt.h>


// ===========================================================
//	File Scope Variables
// ===========================================================
//

// ===========================================================
//	Function Definitions
// ===========================================================

//-----------------------------------------------------------------------------
// SYSCLK_Init
//-----------------------------------------------------------------------------
//
// This routine initializes the system clock to use the internal oscillator
// at 24.5 MHz multiplied by two using the PLL.
//
void SYSCLK_Init (void)
{
 
}


//-----------------------------------------------------------------------------
// Misc_Init
//-----------------------------------------------------------------------------
void	Misc_Init(void)
{
// MCU Control Register - MCUCR
//	SRE:	1 = External SRAM enable [MCUCR.7 = 0]
//	SRW10:	Wait state select bit, combined with SRW11 bit in XMCRA register [MCUCR.6 = 0]
//	SE:	
//	SM0:	
//	SM1:	
//	SM2:	
//	IVSEL:	
//	IVCE:	
//
 MCUCR = (0<<SRE)|(0<<SRW10)|(0<<SE)|(0<<SM0)
 		|(0<<SM1)|(0<<SM2)|(0<<IVSEL)|(0<<IVCE);		

// External Memory Control Register - XMCRA
//	SRL[2:0]:	Wait state sector limit [XMCRA.[6:4] = 000] (See datasheet)
//	SRW0[1:0]:	Wait state select bits for lower sector [XMCRA.[3:2] = 00]
//					00 = No wait state
//					01 = wait 1 cycle during read/write strobe
//					10 = wait 2 cycle during read/write strobe
//					11 = wait 2 cycle during read/write and 1 cycle before new address
//	SRW11:		Wait state select bit (with SRW10 in MCUCR) for upper sector [XMCRA.1 = 0]
//				[SRW11, SRW10]
//					00 = No wait state
//					01 = wait 1 cycle during read/write strobe
//					10 = wait 2 cycle during read/write strobe
//					11 = wait 2 cycle during read/write and 1 cycle before new address
 XMCRA = (0<<SRL2)|(0<<SRL2)|(0<<SRL2)|(0<<SRW01)
 		|(0<<SRW00)|(0<<SRW11);

// External Memory Control Register - XMCRB
//	XMBK:		1 = Enable external memory bus keeper [XMCRb.7 = 0] 
//	XMM[2:0]:	External memory high mask [XMCRb.[2:0] = 000]
//					000 = 8 bit high address, none port pin released
//					001 = 7 bit high address, PC7 released
//					010 = 6 bit high address, PC7 - PC6 released
//					011 = 5 bit high address, PC7 - PC5 released
//					100 = 4 bit high address, PC7 - PC4 released
//					101 = 3 bit high address, PC7 - PC3 released
//					110 = 2 bit high address, PC7 - PC2 released
//					111 = No address high bit, full Port C released
//
 XMCRB = (0<<XMBK)|(1<<XMM2)|(1<<XMM1)|(1<<XMM0);

// Special Function IO Register - SFIOR
//	TSM:	1 = activates the Timer/Counter Synchronization mode.
//	ACME:	1 = Switch off ADC and ADC multiplxer selects comparator negative input.
//			0 = AIN1 (PE3) connects to comparator negative input.
//	PUD:	1 = Disable port pull-up globally, 0 = enable port pull-up.
//	PSR0:	1 = Reset Timer0 prescaler. Clear by HW if TSM = 0.
//	PSR321:	1 = Reset Timer3/2/1 prescaler simultaneously. Clear by HW if TSM = 0.
//
// SFIOR defaults are all bits 0.
//

 SFIOR = (0<<TSM)|(0<<ACME)|(0<<PUD)|(0<<PSR0)|(0<<PSR321);

// External Interrupt Control Register A – EICRA
//	ISC31, ISC30 - ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
//
//	ISCn1 ISCn0 Description
//		0 0 = The low level of INTn generates an interrupt request.
//		0 1 = Reserved
//		1 0 = The falling edge of INTn generates asynchronously an interrupt request.
//		1 1 = The rising edge of INTn generates asynchronously an interrupt request.
//
//	Falling edge trigs interrupt
 EICRA = (1<<ISC31)|(0<<ISC30)|(1<<ISC21)|(0<<ISC20)
 		|(1<<ISC11)|(0<<ISC10)|(1<<ISC01)|(0<<ISC00);

// External Interrupt Control Register B – EICRB
//	ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
//
//	ISCn1 ISCn0 Description
//		0 0 = The low level of INTn generates an interrupt request.
//		0 1 = Any logical change on INTn generates an interrupt request
//		1 0 = The falling edge between two samples of INTn generates an interrupt request.
//		1 1 = The rising edge between two samples of INTn generates an interrupt request.
 EICRB = (0<<ISC71)|(0<<ISC70)|(0<<ISC61)|(0<<ISC60)
 		|(0<<ISC51)|(0<<ISC50)|(0<<ISC41)|(0<<ISC40); 

// External Interrupt Mask Register – EIMSK
//	INT7 - INT0: External Interrupt Request 7 - 0 Enable. 1 = Enabled
//
 EIMSK = (0<<INT7)|(0<<INT6)|(0<<INT5)|(0<<INT4)
 		|(1<<INT3)|(1<<INT2)|(1<<INT1)|(1<<INT0);
// EIMSK = (0<<INT7)|(0<<INT6)|(0<<INT5)|(0<<INT4)
// 		|(0<<INT3)|(0<<INT2)|(0<<INT1)|(0<<INT0);

// External Interrupt Flag Register – EIFR
//	INTF7 - INTF0: External Interrupt Flags 7 - 0
//
 EIFR = (1<<INTF7)|(1<<INTF6)|(1<<INTF5)|(1<<INTF4)
 		|(1<<INTF3)|(1<<INTF2)|(1<<INTF1)|(1<<INTF0);

}

//-----------------------------------------------------------------------------
// PORT_Init
//-----------------------------------------------------------------------------
//
// This routine configures the crossbar and GPIO ports.
//
void Port_Init(void)
{

//  Note: pull-up function requires PUD in SFIOR (SFIOR.2) to be zero (default value).
//		(See Misc_Init())
//
//  PORTx (input):  1=pull-up on, 0=pull-up off
//  PORTx (output): 1=output high (source), 0=output low (sink)
//  DDRx: 1=output, 0=input

//  PORTx and DDRx defaults are all bits zero.

 // Port A default to output mode 
 PORTA = 
 	(0<<PA7)|(0<<PA6)|(0<<PA5)|(0<<PA4)|(0<<PA3)|(0<<PA2)|(0<<PA1)|(0<<PA0);
 DDRA = 
 	  (0<<DDA7)|(0<<DDA6)|(0<<DDA5)|(0<<DDA4)
 	|(0<<DDA3)|(0<<DDA2)|(0<<DDA1)|(0<<DDA0);

// PB7: 
// PB6: 
// PB5: 
// PB4: 
// PB3: 
// PB2: 
// PB1: 
// PB0: Output, LCD WR control

 PORTB = 
 	(0<<PB7)|(0<<PB6)|(0<<PB5)|(0<<PB4)|(0<<PB3)|(0<<PB2)|(0<<PB1)|(0<<PB0);
 DDRB = 
 	  (0<<DDB7)|(0<<DDB6)|(0<<DDB5)|(0<<DDB4)
 	|(0<<DDB3)|(0<<DDB2)|(0<<DDB1)|(1<<DDB0);

 // PC[7:0]:	LCD data port
 PORTC = 
 	(0<<PC7)|(0<<PC6)|(0<<PC5)|(0<<PC4)|(0<<PC3)|(0<<PC2)|(0<<PC1)|(0<<PC0);
 DDRC = 
 	  (1<<DDC7)|(1<<DDC6)|(1<<DDC5)|(1<<DDC4)
 	|(1<<DDC3)|(1<<DDC2)|(1<<DDC1)|(1<<DDC0);

 // PD7:	
 // PD6:	
 // PD5:	
 // PD4:	
 // PD3:	
 // PD2:	Input, key scan, ROW3
 // PD1:	Input, key scan, ROW2
 // PD0:	Input, key scan, ROW1
 // PD0:	Input, key scan, ROW0
 PORTD = 
 	(0<<PD7)|(0<<PD6)|(0<<PD5)|(0<<PD4)|(1<<PD3)|(1<<PD2)|(1<<PD1)|(1<<PD0);
 DDRD = 
 	  (0<<DDD7)|(0<<DDD6)|(0<<DDD5)|(0<<DDD4)
 	|(0<<DDD3)|(0<<DDD2)|(0<<DDD1)|(0<<DDD0);

 // PE7:	
 // PE6:	
 // PE5:	
 // PE4:	
 // PE3:	
 // PE2:	
 // PE1:	
 // PE0:	
 PORTE = 
 	(0<<PE7)|(0<<PE6)|(0<<PE5)|(0<<PE4)|(0<<PE3)|(0<<PE2)|(0<<PE1)|(0<<PE0);
 DDRE = 
 	  (0<<DDE7)|(0<<DDE6)|(0<<DDE5)|(0<<DDE4)
 	|(0<<DDE3)|(0<<DDE2)|(0<<DDE1)|(0<<DDE0);

 // PF7:	Output, key scan, COL2
 // PF6:	Output, key scan, COL1
 // PF5:	Output, key scan, COL0
 // PF4:	
 // PF3:	
 // PF2:	
 // PF1:	
 // PF0:	
 PORTF = 
 	(0<<PF7)|(0<<PF6)|(0<<PF5)|(0<<PF4)|(0<<PF3)|(0<<PF2)|(0<<PF1)|(0<<PF0);
 DDRF = 
 	  (1<<DDF7)|(1<<DDF6)|(1<<DDF5)|(0<<DDF4)
 	|(0<<DDF3)|(0<<DDF2)|(0<<DDF1)|(0<<DDF0);

// PG4: Output, LCD E control
// PG3: Output, LCD DI control
// PG2: Output, LCD RES control
// PG1: Output, LCD CS2 control
// PG0: Output, LCD CS1 control

 PORTG = 
 	(0<<PG4)|(0<<PG3)|(0<<PG2)|(0<<PG1)|(0<<PG0);
 DDRG = 
 	(1<<DDG4)|(1<<DDG3)|(1<<DDG2)|(1<<DDG1)|(1<<DDG0);

}

//-----------------------------------------------------------------------------
// UART0_Init
//-----------------------------------------------------------------------------
//
void Uart0_Init (void)
{
 // UCSR0A - USART Control and Status Register A
 //	RXC0:	1 = Receive complete [UCSR0A.7]
 //	TXC0:	1 = Transmit complete [UCSR0A.6]
 //	UDRE0:	1 = USART Data Register Empty [UCSR0A.5]
 //	FE0:		1 = Frame Error [UCSR0A.4]
 //	DOR0:	1 = Data Over Run [UCSR0A.3]
 //	UPE0:	1 = USART Parity Error [UCSR0A.2]
 //	U2X0:	1 = Double USART transmission speed (for asynchronous only) [UCSR0A.1]
 //	MPCM0:	1 = Multiprocessor Communication Mode [UCSR0A.0]
 //
 // UCSR0A defaults are all bits zero.
 UCSR0A = (0<<TXC0)|(0<<U2X0)|(0<<MPCM0);

 // UCSR0B - USART Control and Status Register B
 //	RXCIE0:	1 = Receive complete interrupt enable [UCSR0B.7]
 //	TXCIE0:	1 = Transmit complete interrupt enable [UCSR0B.6]
 //	UDRIE0:	1 = USART Data Register Empty interrupt enable [UCSR0B.5]
 //	RXEN0:	1 = Receiver enable [UCSR0B.4]
 //	TXEN0:	1 = Transmitter enable [UCSR0B.3]
 //	UCSZ02:	Character size, combined with UCSZ0.[1:0] in UCSR0C [UCSR0B.2]
 //	RXB80:	1 = Receive Date Bit 8 [UCSR0B.1]
 //	TXB80:	1 = Transmit Date Bit 8 [UCSR0B.0]
 //
 // UCSR0B defaults are all bits zero.

 // -- Enable receiver
 // -- Enable transmitter
 UCSR0B = (0<<RXCIE0)|(0<<TXCIE0)|(0<<UDRIE0)|(1<<RXEN0)
 			|(1<<TXEN0)|(0<<UCSZ02)|(0<<TXB80);

 // UCSR0C - USART Control and Status Register C
 //	UMSEL0:	1 = Asynchronous, 0 = Synchronous [UCSR0C.6]
 //	UPM0.[1:0]:	Parity Mode [UCSR0C.[5:4]]
 //				00 = Disabled
 //				01 = Reserved
 //				10 = Enabled, even parity
 //				11 = Enabled, odd parity
 //	USBS0:	Stop bit select, 0 = 1 stop bit, 1 = 2 stop bits [UCSR0C.3]
 //	UCSZ0.[1:0]:	Character size, combined with UCSZ02 in UCSR0B [UCSR0C.2]
 //				000 = 5-bit
 //				001 = 6-bit
 //				010 = 7-bit
 //				011 = 8-bit
 //				100 = Reserved
 //				101 = Reserved
 //				110 = Reserved
 //				111 = 9-bit
 //	UCPOL0:	Clock pority, for synchronous mode only [UCSR0C.0] (See datasheet)
 //
 UCSR0C = (0<<UMSEL0)|(0<<UPM01)|(0<<UPM00)|(0<<USBS0)
 			|(1<<UCSZ01)|(1<<UCSZ00)|(0<<UCPOL0);

// Setup baudrate
 UBRR0H = (((F_CPU / 16) / Uart0_Baud) - 1) >> 8;
 UBRR0L = (((F_CPU / 16) / Uart0_Baud) - 1) & 0x00FF;
 
}


//-----------------------------------------------------------------------------
// UART1_Init
//-----------------------------------------------------------------------------
//
void Uart1_Init (void)
{
 // UCSR1A - USART Control and Status Register A
 //	RXC1:	1 = Receive complete [UCSR1A.7]
 //	TXC1:	1 = Transmit complete [UCSR1A.6]