de2_synthesizer.map.qmsg

build synthesizer on a de2 dev fpga board

{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(12) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(12): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 12 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(13) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(13): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 13 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(14) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(14): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 14 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(15) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(15): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 15 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(16) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(16): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 16 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(17) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(17): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 17 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(18) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(18): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 18 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(19) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(19): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 19 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(20) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(20): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 20 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(21) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(21): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 21 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(22) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(22): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 22 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(23) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(23): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 23 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(24) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(24): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 24 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(25) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(25): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 25 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(26) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(26): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 26 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(27) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(27): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 27 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(28) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(28): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 28 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(29) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(29): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 29 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(30) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(30): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 30 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(31) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(31): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 31 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(32) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(32): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 32 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(33) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(33): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 33 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(34) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(34): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 34 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(35) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(35): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 35 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(36) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(36): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 36 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(37) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(37): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 37 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(38) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(38): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 38 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(39) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(39): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 39 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(40) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(40): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 40 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 wave_gen_ramp.v(41) " "Warning (10229): Verilog HDL Expression warning at wave_gen_ramp.v(41): truncated literal to match 16 bits" {  } { { "wave_gen_ramp.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/wave_gen_ramp.v" 41 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}