de2_synthesizer.hier_info

build synthesizer on a de2 dev fpga board

oSEG0[6] <= SEG7_LUT:u0.port0
oSEG1[0] <= SEG7_LUT:u1.port0
oSEG1[1] <= SEG7_LUT:u1.port0
oSEG1[2] <= SEG7_LUT:u1.port0
oSEG1[3] <= SEG7_LUT:u1.port0
oSEG1[4] <= SEG7_LUT:u1.port0
oSEG1[5] <= SEG7_LUT:u1.port0
oSEG1[6] <= SEG7_LUT:u1.port0
oSEG2[0] <= SEG7_LUT:u2.port0
oSEG2[1] <= SEG7_LUT:u2.port0
oSEG2[2] <= SEG7_LUT:u2.port0
oSEG2[3] <= SEG7_LUT:u2.port0
oSEG2[4] <= SEG7_LUT:u2.port0
oSEG2[5] <= SEG7_LUT:u2.port0
oSEG2[6] <= SEG7_LUT:u2.port0
oSEG3[0] <= SEG7_LUT:u3.port0
oSEG3[1] <= SEG7_LUT:u3.port0
oSEG3[2] <= SEG7_LUT:u3.port0
oSEG3[3] <= SEG7_LUT:u3.port0
oSEG3[4] <= SEG7_LUT:u3.port0
oSEG3[5] <= SEG7_LUT:u3.port0
oSEG3[6] <= SEG7_LUT:u3.port0
oSEG4[0] <= SEG7_LUT:u4.port0
oSEG4[1] <= SEG7_LUT:u4.port0
oSEG4[2] <= SEG7_LUT:u4.port0
oSEG4[3] <= SEG7_LUT:u4.port0
oSEG4[4] <= SEG7_LUT:u4.port0
oSEG4[5] <= SEG7_LUT:u4.port0
oSEG4[6] <= SEG7_LUT:u4.port0
oSEG5[0] <= SEG7_LUT:u5.port0
oSEG5[1] <= SEG7_LUT:u5.port0
oSEG5[2] <= SEG7_LUT:u5.port0
oSEG5[3] <= SEG7_LUT:u5.port0
oSEG5[4] <= SEG7_LUT:u5.port0
oSEG5[5] <= SEG7_LUT:u5.port0
oSEG5[6] <= SEG7_LUT:u5.port0
oSEG6[0] <= SEG7_LUT:u6.port0
oSEG6[1] <= SEG7_LUT:u6.port0
oSEG6[2] <= SEG7_LUT:u6.port0
oSEG6[3] <= SEG7_LUT:u6.port0
oSEG6[4] <= SEG7_LUT:u6.port0
oSEG6[5] <= SEG7_LUT:u6.port0
oSEG6[6] <= SEG7_LUT:u6.port0
oSEG7[0] <= SEG7_LUT:u7.port0
oSEG7[1] <= SEG7_LUT:u7.port0
oSEG7[2] <= SEG7_LUT:u7.port0
oSEG7[3] <= SEG7_LUT:u7.port0
oSEG7[4] <= SEG7_LUT:u7.port0
oSEG7[5] <= SEG7_LUT:u7.port0
oSEG7[6] <= SEG7_LUT:u7.port0
iDIG[0] => iDIG[0]~31.IN1
iDIG[1] => iDIG[1]~30.IN1
iDIG[2] => iDIG[2]~29.IN1
iDIG[3] => iDIG[3]~28.IN1
iDIG[4] => iDIG[4]~27.IN1
iDIG[5] => iDIG[5]~26.IN1
iDIG[6] => iDIG[6]~25.IN1
iDIG[7] => iDIG[7]~24.IN1
iDIG[8] => iDIG[8]~23.IN1
iDIG[9] => iDIG[9]~22.IN1
iDIG[10] => iDIG[10]~21.IN1
iDIG[11] => iDIG[11]~20.IN1
iDIG[12] => iDIG[12]~19.IN1
iDIG[13] => iDIG[13]~18.IN1
iDIG[14] => iDIG[14]~17.IN1
iDIG[15] => iDIG[15]~16.IN1
iDIG[16] => iDIG[16]~15.IN1
iDIG[17] => iDIG[17]~14.IN1
iDIG[18] => iDIG[18]~13.IN1
iDIG[19] => iDIG[19]~12.IN1
iDIG[20] => iDIG[20]~11.IN1
iDIG[21] => iDIG[21]~10.IN1
iDIG[22] => iDIG[22]~9.IN1
iDIG[23] => iDIG[23]~8.IN1
iDIG[24] => iDIG[24]~7.IN1
iDIG[25] => iDIG[25]~6.IN1
iDIG[26] => iDIG[26]~5.IN1
iDIG[27] => iDIG[27]~4.IN1
iDIG[28] => iDIG[28]~3.IN1
iDIG[29] => iDIG[29]~2.IN1
iDIG[30] => iDIG[30]~1.IN1
iDIG[31] => iDIG[31]~0.IN1


|DE2_synthesizer|SEG7_LUT_8:u0|SEG7_LUT:u0
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_synthesizer|SEG7_LUT_8:u0|SEG7_LUT:u1
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_synthesizer|SEG7_LUT_8:u0|SEG7_LUT:u2
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_synthesizer|SEG7_LUT_8:u0|SEG7_LUT:u3
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_synthesizer|SEG7_LUT_8:u0|SEG7_LUT:u4
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_synthesizer|SEG7_LUT_8:u0|SEG7_LUT:u5
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_synthesizer|SEG7_LUT_8:u0|SEG7_LUT:u6
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_synthesizer|SEG7_LUT_8:u0|SEG7_LUT:u7
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_synthesizer|I2C_AV_Config:u7
iCLK => mI2C_CTRL_CLK.CLK
iCLK => mI2C_CLK_DIV[15].CLK
iCLK => mI2C_CLK_DIV[14].CLK
iCLK => mI2C_CLK_DIV[13].CLK
iCLK => mI2C_CLK_DIV[12].CLK
iCLK => mI2C_CLK_DIV[11].CLK
iCLK => mI2C_CLK_DIV[10].CLK
iCLK => mI2C_CLK_DIV[9].CLK
iCLK => mI2C_CLK_DIV[8].CLK
iCLK => mI2C_CLK_DIV[7].CLK
iCLK => mI2C_CLK_DIV[6].CLK
iCLK => mI2C_CLK_DIV[5].CLK
iCLK => mI2C_CLK_DIV[4].CLK
iCLK => mI2C_CLK_DIV[3].CLK
iCLK => mI2C_CLK_DIV[2].CLK
iCLK => mI2C_CLK_DIV[1].CLK
iCLK => mI2C_CLK_DIV[0].CLK
iRST_N => iRST_N~0.IN1
o_I2C_END <= o_I2C_END~reg0.DB_MAX_OUTPUT_PORT_TYPE
I2C_SCLK <= I2C_Controller:u0.I2C_SCLK
I2C_SDAT <= I2C_Controller:u0.I2C_SDAT


|DE2_synthesizer|I2C_AV_Config:u7|I2C_Controller:u0
CLOCK => SD_COUNTER[5]~reg0.CLK
CLOCK => SD_COUNTER[4]~reg0.CLK
CLOCK => SD_COUNTER[3]~reg0.CLK
CLOCK => SD_COUNTER[2]~reg0.CLK
CLOCK => SD_COUNTER[1]~reg0.CLK
CLOCK => SD_COUNTER[0]~reg0.CLK
CLOCK => SCLK.CLK
CLOCK => SDO~reg0.CLK
CLOCK => ACK1.CLK
CLOCK => ACK2.CLK
CLOCK => ACK3.CLK
CLOCK => END~reg0.CLK
CLOCK => SD[23].CLK
CLOCK => SD[22].CLK
CLOCK => SD[21].CLK
CLOCK => SD[20].CLK
CLOCK => SD[19].CLK
CLOCK => SD[18].CLK
CLOCK => SD[17].CLK
CLOCK => SD[16].CLK
CLOCK => SD[15].CLK
CLOCK => SD[14].CLK
CLOCK => SD[13].CLK
CLOCK => SD[12].CLK
CLOCK => SD[11].CLK
CLOCK => SD[10].CLK
CLOCK => SD[9].CLK
CLOCK => SD[8].CLK
CLOCK => SD[7].CLK
CLOCK => SD[6].CLK
CLOCK => SD[5].CLK
CLOCK => SD[4].CLK
CLOCK => SD[3].CLK
CLOCK => SD[2].CLK
CLOCK => SD[1].CLK
CLOCK => SD[0].CLK
CLOCK => comb~1.DATAB
I2C_SCLK <= comb~2.DB_MAX_OUTPUT_PORT_TYPE
I2C_SDAT <= I2C_SDAT~0
I2C_DATA[0] => SD~23.DATAB
I2C_DATA[1] => SD~22.DATAB
I2C_DATA[2] => SD~21.DATAB
I2C_DATA[3] => SD~20.DATAB
I2C_DATA[4] => SD~19.DATAB
I2C_DATA[5] => SD~18.DATAB
I2C_DATA[6] => SD~17.DATAB
I2C_DATA[7] => SD~16.DATAB
I2C_DATA[8] => SD~15.DATAB
I2C_DATA[9] => SD~14.DATAB
I2C_DATA[10] => SD~13.DATAB
I2C_DATA[11] => SD~12.DATAB
I2C_DATA[12] => SD~11.DATAB
I2C_DATA[13] => SD~10.DATAB
I2C_DATA[14] => SD~9.DATAB
I2C_DATA[15] => SD~8.DATAB
I2C_DATA[16] => SD~7.DATAB
I2C_DATA[17] => SD~6.DATAB
I2C_DATA[18] => SD~5.DATAB
I2C_DATA[19] => SD~4.DATAB
I2C_DATA[20] => SD~3.DATAB
I2C_DATA[21] => SD~2.DATAB
I2C_DATA[22] => SD~1.DATAB
I2C_DATA[23] => SD~0.DATAB
GO => SD_COUNTER~11.OUTPUTSELECT
GO => SD_COUNTER~10.OUTPUTSELECT
GO => SD_COUNTER~9.OUTPUTSELECT
GO => SD_COUNTER~8.OUTPUTSELECT
GO => SD_COUNTER~7.OUTPUTSELECT
GO => SD_COUNTER~6.OUTPUTSELECT
END <= END~reg0.DB_MAX_OUTPUT_PORT_TYPE
W_R => ~NO_FANOUT~
ACK <= comb~4.DB_MAX_OUTPUT_PORT_TYPE
RESET => SD_COUNTER[0]~reg0.PRESET
RESET => SD_COUNTER[1]~reg0.PRESET
RESET => SD_COUNTER[2]~reg0.PRESET
RESET => SD_COUNTER[3]~reg0.PRESET
RESET => SD_COUNTER[4]~reg0.PRESET
RESET => SD_COUNTER[5]~reg0.PRESET
RESET => SCLK.PRESET
RESET => SDO~reg0.PRESET
RESET => ACK1.ACLR
RESET => ACK2.ACLR
RESET => ACK3.ACLR
RESET => END~reg0.PRESET
RESET => SD[0].ENA
RESET => SD[23].ENA
RESET => SD[22].ENA
RESET => SD[21].ENA
RESET => SD[20].ENA
RESET => SD[19].ENA
RESET => SD[18].ENA
RESET => SD[17].ENA
RESET => SD[16].ENA
RESET => SD[15].ENA
RESET => SD[14].ENA
RESET => SD[13].ENA
RESET => SD[12].ENA
RESET => SD[11].ENA
RESET => SD[10].ENA
RESET => SD[9].ENA
RESET => SD[8].ENA
RESET => SD[7].ENA
RESET => SD[6].ENA
RESET => SD[5].ENA
RESET => SD[4].ENA
RESET => SD[3].ENA
RESET => SD[2].ENA
RESET => SD[1].ENA
SD_COUNTER[0] <= SD_COUNTER[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD_COUNTER[1] <= SD_COUNTER[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD_COUNTER[2] <= SD_COUNTER[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD_COUNTER[3] <= SD_COUNTER[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD_COUNTER[4] <= SD_COUNTER[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD_COUNTER[5] <= SD_COUNTER[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SDO <= SDO~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_synthesizer|VGA_Audio_PLL:u1
areset => areset~0.IN1
inclk0 => sub_wire5[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
c2 <= altpll:altpll_component.clk


|DE2_synthesizer|VGA_Audio_PLL:u1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~2.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1]~1.DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|DE2_synthesizer|demo_sound1:dd1
clock => step[15].CLK
clock => step[14].CLK
clock => step[13].CLK
clock => step[12].CLK
clock => step[11].CLK
clock => step[10].CLK
clock => step[9].CLK
clock => step[8].CLK
clock => step[7].CLK
clock => step[6].CLK
clock => step[5].CLK
clock => step[4].CLK
clock => step[3].CLK
clock => step[2].CLK
clock => step[1].CLK
clock => step[0].CLK
clock => st[5].CLK
clock => st[4].CLK
clock => st[3].CLK
clock => st[2].CLK
clock => st[1].CLK
clock => st[0].CLK
clock => tr.CLK
clock => tmp[15].CLK
clock => tmp[14].CLK
clock => tmp[13].CLK
clock => tmp[12].CLK
clock => tmp[11].CLK
clock => tmp[10].CLK
clock => tmp[9].CLK
clock => tmp[8].CLK
clock => tmp[7].CLK
clock => tmp[6].CLK
clock => tmp[5].CLK
clock => tmp[4].CLK
clock => tmp[3].CLK
clock => tmp[2].CLK
clock => tmp[1].CLK
clock => tmp[0].CLK
clock => go_end.CLK
key_code[0] <= key_code~7.DB_MAX_OUTPUT_PORT_TYPE
key_code[1] <= key_code~6.DB_MAX_OUTPUT_PORT_TYPE