📄 de2_synthesizer.fit.rpt
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Fitter report for DE2_synthesizer
Thu Nov 16 09:02:34 2006
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Netlist Optimizations
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. Bidir Pins
10. I/O Bank Usage
11. All Package Pins
12. PLL Summary
13. PLL Usage
14. Clock Delay Control Summary
15. Output Pin Default Load For Reported TCO
16. Fitter Resource Utilization by Entity
17. Delay Chain Summary
18. Pad To Core Delay Chain Fanout
19. Control Signals
20. Global & Other Fast Signals
21. Non-Global High Fan-Out Signals
22. Fitter RAM Summary
23. Interconnect Usage Summary
24. LAB Logic Elements
25. LAB-wide Signals
26. LAB Signals Sourced
27. LAB Signals Sourced Out
28. LAB Distinct Inputs
29. Fitter Device Options
30. Fitter Messages
31. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+-----------------------------------------------+
; Fitter Status ; Successful - Thu Nov 16 09:02:33 2006 ;
; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name ; DE2_synthesizer ;
; Top-level Entity Name ; DE2_synthesizer ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Total logic elements ; 1,499 / 33,216 ( 5 % ) ;
; Total registers ; 342 ;
; Total pins ; 423 / 475 ( 89 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,024 / 483,840 ( < 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
+------------------------------------+-----------------------------------------------+
+------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP2C35F672C6 ; ;
; Use smart compilation ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Stratix II/Cyclone II ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Always Enable Input Buffers ; Off ; Off ;
+------------------------------------------------+--------------------------------+--------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations ;
+-------------------------------------------+-----------------+------------------+---------------------+-----------+-------------------------------------------------------------------------------+------------------+
; Node ; Action ; Operation ; Reason ; Node Port ; Destination Node ; Destination Port ;
+-------------------------------------------+-----------------+------------------+---------------------+-----------+-------------------------------------------------------------------------------+------------------+
; I2C_AV_Config:u7|I2C_Controller:u0|SD[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[15] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[14] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[13] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[12] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[11] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[10] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[9] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[8] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[7] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[6] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[10] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[5] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[11] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[4] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[12] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[3] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[13] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[2] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[14] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[1] ; PORTADATAOUT ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD[15] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|q_a[0] ; PORTADATAOUT ;
+-------------------------------------------+-----------------+------------------+---------------------+-----------+-------------------------------------------------------------------------------+------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/User/⌨️ 快捷键说明
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