de2_synthesizer.tan.rpt

build synthesizer on a de2 dev fpga board

; Worst-case th                                                 ; N/A                                      ; None                             ; -0.669 ns                        ; I2C_SDAT                           ; I2C_AV_Config:u7|I2C_Controller:u0|ACK3 ; --                                             ; CLOCK_50                                       ; 0            ;
; Clock Setup: 'VGA_Audio_PLL:u1|altpll:altpll_component|_clk1' ; 51.878 ns                                ; 18.00 MHz ( period = 55.555 ns ) ; 271.96 MHz ( period = 3.677 ns ) ; adio_codec:ad1|ramp2[1]            ; adio_codec:ad1|ramp2[4]                 ; VGA_Audio_PLL:u1|altpll:altpll_component|_clk1 ; VGA_Audio_PLL:u1|altpll:altpll_component|_clk1 ; 0            ;
; Clock Setup: 'CLOCK_50'                                       ; N/A                                      ; None                             ; 28.42 MHz ( period = 35.182 ns ) ; demo_sound1:dd1|TT[6]              ; demo_sound1:dd1|tmp[3]                  ; CLOCK_50                                       ; CLOCK_50                                       ; 0            ;
; Clock Setup: 'PS2_CLK'                                        ; N/A                                      ; None                             ; 116.78 MHz ( period = 8.563 ns ) ; PS2_KEYBOARD:keyboard|key2_code[4] ; PS2_KEYBOARD:keyboard|key2_code[5]      ; PS2_CLK                                        ; PS2_CLK                                        ; 0            ;
; Clock Hold: 'VGA_Audio_PLL:u1|altpll:altpll_component|_clk1'  ; 0.391 ns                                 ; 18.00 MHz ( period = 55.555 ns ) ; N/A                              ; adio_codec:ad1|SEL_Cont[3]         ; adio_codec:ad1|SEL_Cont[3]              ; VGA_Audio_PLL:u1|altpll:altpll_component|_clk1 ; VGA_Audio_PLL:u1|altpll:altpll_component|_clk1 ; 0            ;
; Clock Hold: 'CLOCK_50'                                        ; Not operational: Clock Skew > Data Delay ; None                             ; N/A                              ; demo_sound1:dd1|step[0]            ; demo_sound1:dd1|TT[0]                   ; CLOCK_50                                       ; CLOCK_50                                       ; 256          ;
; Clock Hold: 'PS2_CLK'                                         ; Not operational: Clock Skew > Data Delay ; None                             ; N/A                              ; PS2_KEYBOARD:keyboard|keycode_o[7] ; PS2_KEYBOARD:keyboard|scandata[7]       ; PS2_CLK                                        ; PS2_CLK                                        ; 33           ;
; Total number of failed paths                                  ;                                          ;                                  ;                                  ;                                    ;                                         ;                                                ;                                                ; 289          ;
+---------------------------------------------------------------+------------------------------------------+----------------------------------+----------------------------------+------------------------------------+-----------------------------------------+------------------------------------------------+------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                 ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; VGA_Audio_PLL:u1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 18.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 2                     ; 3                   ; -2.384 ns ;              ;
; CLOCK_27                                       ;                    ; User Pin   ; 27.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; PS2_CLK                                        ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; CLOCK_50                                       ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'VGA_Audio_PLL:u1|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+--------------------------+--------------------------+------------------------------------------------+------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                     ; To                       ; From Clock                                     ; To Clock                                       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;