prev_cmp_de2_synthesizer.qmsg

build synthesizer on a de2 dev fpga board

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(77) " "Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(77): truncated value with size 32 to match size of target (1)" {  } { { "I2C_Controller.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/I2C_Controller.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_Controller.v(90) " "Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)" {  } { { "I2C_Controller.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/I2C_Controller.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "VGA_Audio_PLL.v 1 1 " "Warning: Using design file VGA_Audio_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_Audio_PLL " "Info: Found entity 1: VGA_Audio_PLL" {  } { { "VGA_Audio_PLL.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/VGA_Audio_PLL.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_Audio_PLL VGA_Audio_PLL:u1 " "Info: Elaborating entity \"VGA_Audio_PLL\" for hierarchy \"VGA_Audio_PLL:u1\"" {  } { { "DE2_synthesizer.v" "u1" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/DE2_synthesizer.v" 368 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/71/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 462 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll VGA_Audio_PLL:u1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"VGA_Audio_PLL:u1\|altpll:altpll_component\"" {  } { { "VGA_Audio_PLL.v" "altpll_component" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/VGA_Audio_PLL.v" 89 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "VGA_Audio_PLL:u1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"VGA_Audio_PLL:u1\|altpll:altpll_component\"" {  } { { "VGA_Audio_PLL.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/VGA_Audio_PLL.v" 89 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "demo_sound1.v 1 1 " "Warning: Using design file demo_sound1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 demo_sound1 " "Info: Found entity 1: demo_sound1" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "demo_sound1 demo_sound1:dd1 " "Info: Elaborating entity \"demo_sound1\" for hierarchy \"demo_sound1:dd1\"" {  } { { "DE2_synthesizer.v" "dd1" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/DE2_synthesizer.v" 396 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 demo_sound1.v(26) " "Warning (10230): Verilog HDL assignment warning at demo_sound1.v(26): truncated value with size 32 to match size of target (6)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 demo_sound1.v(27) " "Warning (10230): Verilog HDL assignment warning at demo_sound1.v(27): truncated value with size 32 to match size of target (6)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 27 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 demo_sound1.v(28) " "Warning (10230): Verilog HDL assignment warning at demo_sound1.v(28): truncated value with size 32 to match size of target (6)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 demo_sound1.v(29) " "Warning (10230): Verilog HDL assignment warning at demo_sound1.v(29): truncated value with size 32 to match size of target (6)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 demo_sound1.v(30) " "Warning (10230): Verilog HDL assignment warning at demo_sound1.v(30): truncated value with size 32 to match size of target (16)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 demo_sound1.v(50) " "Warning (10230): Verilog HDL assignment warning at demo_sound1.v(50): truncated value with size 32 to match size of target (16)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "demo_sound1.v(63) " "Warning (10270): Verilog HDL Case Statement warning at demo_sound1.v(63): incomplete case statement has no default case item" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 63 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "TT demo_sound1.v(62) " "Warning (10240): Verilog HDL Always Construct warning at demo_sound1.v(62): inferring latch(es) for variable \"TT\", which holds its previous value in one or more paths through the always construct" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 demo_sound1.v(130) " "Warning (10230): Verilog HDL assignment warning at demo_sound1.v(130): truncated value with size 32 to match size of target (16)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TT\[0\] demo_sound1.v(62) " "Info (10041): Inferred latch for \"TT\[0\]\" at demo_sound1.v(62)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TT\[1\] demo_sound1.v(62) " "Info (10041): Inferred latch for \"TT\[1\]\" at demo_sound1.v(62)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TT\[2\] demo_sound1.v(62) " "Info (10041): Inferred latch for \"TT\[2\]\" at demo_sound1.v(62)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TT\[3\] demo_sound1.v(62) " "Info (10041): Inferred latch for \"TT\[3\]\" at demo_sound1.v(62)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TT\[4\] demo_sound1.v(62) " "Info (10041): Inferred latch for \"TT\[4\]\" at demo_sound1.v(62)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TT\[5\] demo_sound1.v(62) " "Info (10041): Inferred latch for \"TT\[5\]\" at demo_sound1.v(62)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TT\[6\] demo_sound1.v(62) " "Info (10041): Inferred latch for \"TT\[6\]\" at demo_sound1.v(62)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TT\[7\] demo_sound1.v(62) " "Info (10041): Inferred latch for \"TT\[7\]\" at demo_sound1.v(62)" {  } { { "demo_sound1.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound1.v" 62 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "demo_sound2.v 1 1 " "Warning: Using design file demo_sound2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 demo_sound2 " "Info: Found entity 1: demo_sound2" {  } { { "demo_sound2.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "demo_sound2 demo_sound2:dd2 " "Info: Elaborating entity \"demo_sound2\" for hierarchy \"demo_sound2:dd2\"" {  } { { "DE2_synthesizer.v" "dd2" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/DE2_synthesizer.v" 406 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 demo_sound2.v(26) " "Warning (10230): Verilog HDL assignment warning at demo_sound2.v(26): truncated value with size 32 to match size of target (6)" {  } { { "demo_sound2.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound2.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 demo_sound2.v(27) " "Warning (10230): Verilog HDL assignment warning at demo_sound2.v(27): truncated value with size 32 to match size of target (6)" {  } { { "demo_sound2.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound2.v" 27 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 demo_sound2.v(28) " "Warning (10230): Verilog HDL assignment warning at demo_sound2.v(28): truncated value with size 32 to match size of target (6)" {  } { { "demo_sound2.v" "" { Text "C:/Documents and Settings/eyal/Desktop/DE2_synthesizer/DE2_synthesizer/demo_sound2.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 demo_sound2.v(29) " "Warning (10230): Verilog HDL assignment warning at demo_sound2.v(29): truncated value with size 32 to match size of target