📄 compile.log

📁 d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

💻 LOG

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 Compilation...
 File: .\src\VHDL code3.vhd
Error:  COMP96_0018:VHDL code3.vhd : (4, 8): Identifier expected.
Error:  COMP96_0016:VHDL code3.vhd : (4, 9): Design unit declaration expected.
Error:  COMP96_0018:VHDL code3.vhd : (9, 26): Identifier expected.
Error:  COMP96_0016:VHDL code3.vhd : (9, 27): Design unit declaration expected.
 Compile failure 4 Errors 0 Warnings  Analysis time :  0.0 [s]
 Compilation...
 File: .\src\VHDL code3.vhd
Error:  COMP96_0018:VHDL code3.vhd : (4, 8): Identifier expected.
Error:  COMP96_0016:VHDL code3.vhd : (4, 9): Design unit declaration expected.
Error:  COMP96_0018:VHDL code3.vhd : (9, 26): Identifier expected.
Error:  COMP96_0016:VHDL code3.vhd : (9, 27): Design unit declaration expected.
 Compile failure 4 Errors 0 Warnings  Analysis time :  0.0 [s]
 Compilation...
 File: .\src\VHDL code3.vhd
Error:  COMP96_0018:VHDL code3.vhd : (4, 8): Identifier expected.
Error:  COMP96_0016:VHDL code3.vhd : (4, 9): Design unit declaration expected.
Error:  COMP96_0018:VHDL code3.vhd : (9, 26): Identifier expected.
Error:  COMP96_0016:VHDL code3.vhd : (9, 27): Design unit declaration expected.
 Compile failure 4 Errors 0 Warnings  Analysis time :  0.0 [s]
 Compilation...
 File: .\src\VHDL code3.vhd
Error:  COMP96_0018:VHDL code3.vhd : (4, 8): Identifier expected.
Error:  COMP96_0016:VHDL code3.vhd : (4, 9): Design unit declaration expected.
Error:  COMP96_0018:VHDL code3.vhd : (9, 26): Identifier expected.
Error:  COMP96_0016:VHDL code3.vhd : (9, 27): Design unit declaration expected.
 Compile failure 4 Errors 0 Warnings  Analysis time :  0.0 [s]

💿 文件大小 592 K

👤 上传用户 liu4052032

📂 所属分类 VHDL/FPGA/Verilog

🏷️ 相关标签

#using #flip #flop #creating

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