synchronouscounter.erf

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

MESSAGE "File: .\src\VHDL code8.vhd" 
MESSAGE "Compile Entity "counter"" 
MESSAGE "Compile Architecture "archi" of Entity "counter"" 
ERROR COMP96_0046: "Sequential statement expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0019: "Keyword "end" expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0019: "Keyword "if" expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0015: "';' expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0019: "Keyword "end" expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0019: "Keyword "process" expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0015: "';' expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0019: "Keyword "end" expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0015: "';' expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 276
ERROR COMP96_0016: "Design unit declaration expected." "c:\my designs\synchronouscounter\src\VHDL code8.vhd" 2 278
MESSAGE "Compile failure 10 Errors 0 Warnings  Analysis time :  0.0 [s]"