synchronouscounter.mgf

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

01000046 V counter 5 ".\src\VHDL code8.vhd" 715 304 0
12
0
12
00000002
1
.\src\VHDL*code8.vhd
0
0 0 0 0 0 0
1
1
29
0
29
12 ~ ~ 0 0
0
67
0
1
15 ieee std_logic_1164 4 2
0
15 ieee std_logic_1164 0 0
0
0
1
29
0
29
12 ~ ~ 1 1
1
67
0
1
15 ieee std_logic_1164 4 2
0
15 ieee std_logic_1164 0 0
0
0
1
5
512
5
12 ~ ~ 2 0
0
5
1
5
1
15 ieee std_logic_1164 5 3
1
1
1
0
1
1
0
4613937818241073152
0
1
1
0
0
0
1
0
0
1
145
147
1
3
0
0
0
0
1
0
0
1
145
147
1
0
0
0
0
0
0
1
12 ~ ~ 3 0
0
1
15 ieee std_logic_1164 4 2
11
3072 0
0
0
1
5
520
5
12 ~ ~ 3 0
0
2
1
2
1
15 STD STANDARD 75 4
1
1
0
1
1
0
4613937818241073152
0
1
1
0
0
0
1
0
0
1
145
147
1
3
0
0
0
0
1
0
0
1
145
147
1
0
0
0
0
0
0
1
12 ~ ~ 3 0
805371389 0
0
0
1
29
0
29
12 ~ ~ 4 2
2
68
0
1
12 ~ ~ 2 0
0
15 ieee std_logic_1164 5 3
0
0
0
#VLB_VERSION 54
#INFO
counter
E 1238516467.171
5
#ACCESS
std
.
ieee
std_logic_1164 all .
std_logic_unsigned all .
.
#OBJECTS
C 0 29 61 1 . 2
CLR 1 29 151 1 . 2
~std_logic_vector{3~downto~0}~ 2 5 240 1 . 2
~NATURAL~range~3~downto~0~ 3 5 460 1 . 2
Q 4 29 644 1 . 2
#SPECIFICATION 
#END