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d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

Design: 9:50 PM, Tuesday, March 31, 2009
Design: Opening design "c:\my designs\synchronouscounter\synchronouscounter.adf"
Design: Error: C:\My Designs\synchronouscounter\src\VHDL code8.vhd cannot be compiled.
Compilation...
File: .\src\VHDL code8.vhd
Compile Entity "counter"
Compile Architecture "archi" of Entity "counter"
Error: COMP96_0046: VHDL code8.vhd : (2, 276): Sequential statement expected.
Error: COMP96_0019: VHDL code8.vhd : (2, 276): Keyword "end" expected.
Error: COMP96_0019: VHDL code8.vhd : (2, 276): Keyword "if" expected.
Error: COMP96_0015: VHDL code8.vhd : (2, 276): ';' expected.
Error: COMP96_0019: VHDL code8.vhd : (2, 276): Keyword "end" expected.
Error: COMP96_0019: VHDL code8.vhd : (2, 276): Keyword "process" expected.
Error: COMP96_0015: VHDL code8.vhd : (2, 276): ';' expected.
Error: COMP96_0019: VHDL code8.vhd : (2, 276): Keyword "end" expected.
Error: COMP96_0015: VHDL code8.vhd : (2, 276): ';' expected.
Error: COMP96_0016: VHDL code8.vhd : (2, 278): Design unit declaration expected.
Compile failure 10 Errors 0 Warnings  Analysis time :  0.0 [s]