fullsubtractor.erf

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

MESSAGE "File: .\src\VHDL code1.vhd" 
ERROR COMP96_0016: "Design unit declaration expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 2 29
ERROR COMP96_0016: "Design unit declaration expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 2 30
ERROR COMP96_0015: "';' expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 3 1
ERROR COMP96_0016: "Design unit declaration expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 3 8
ERROR COMP96_0016: "Design unit declaration expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 3 17
MESSAGE "Compile Architecture "struc" of Entity "fullsubs"" 
ERROR COMP96_0019: "Keyword "end" expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 8 20
ERROR COMP96_0019: "Keyword "component" expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 8 20
ERROR COMP96_0015: "';' expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 8 20
ERROR COMP96_0019: "Keyword "begin" expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 8 20
ERROR COMP96_0019: "Keyword "end" expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 8 20
ERROR COMP96_0015: "';' expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 8 20
ERROR COMP96_0016: "Design unit declaration expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 8 21
MESSAGE "Compile failure 12 Errors 0 Warnings  Analysis time :  0.0 [s]"