compile.log

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

 Compilation...
 File: .\src\VHDL code1.vhd
Error:  COMP96_0016:VHDL code1.vhd : (2, 29): Design unit declaration expected.
Error:  COMP96_0016:VHDL code1.vhd : (2, 30): Design unit declaration expected.
Error:  COMP96_0015:VHDL code1.vhd : (3, 1): ';' expected.
Error:  COMP96_0016:VHDL code1.vhd : (3, 8): Design unit declaration expected.
Error:  COMP96_0016:VHDL code1.vhd : (3, 17): Design unit declaration expected.
 Compile Architecture "struc" of Entity "fullsubs"
Error:  COMP96_0019:VHDL code1.vhd : (8, 20): Keyword "end" expected.
Error:  COMP96_0019:VHDL code1.vhd : (8, 20): Keyword "component" expected.
Error:  COMP96_0015:VHDL code1.vhd : (8, 20): ';' expected.
Error:  COMP96_0019:VHDL code1.vhd : (8, 20): Keyword "begin" expected.
Error:  COMP96_0019:VHDL code1.vhd : (8, 20): Keyword "end" expected.
Error:  COMP96_0015:VHDL code1.vhd : (8, 20): ';' expected.
Error:  COMP96_0016:VHDL code1.vhd : (8, 21): Design unit declaration expected.
 Compile failure 12 Errors 0 Warnings  Analysis time :  0.0 [s]